In one embodiment, updating and searching of entries in a hardware content-addressable memory is coordinated to provide more searching bandwidth (e.g., for determining packet processing information), including, but not limited to, when vectors are moved among entries to free up desired entry positions for insertion of other vectors. A lookup operation is performed in content-addressable memory entries in a hardware content-addressable memory based on a lookup word to generate a content-addressable memory lookup result. Typically overlapping in time, a matching operation is performed in one or more transitory entries to generate a transitory matching result based on the lookup word. These transitory entries are populated with transitory vectors and have an associated index within the content-addressable memory, with these transitory vectors are subsequently inserted in the content-addressable memory at their associated index positions. A matching result is determined from the content-addressable memory lookup result and the transitory matching result.

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

Apparatus and method for efficient compression block decoding using content-addressable structure for header processing. For example, one embodiment of an apparatus comprises: a header parser to extract a sequence of tokens and corresponding length values from a header of a compression block, the tokens and corresponding length values associated with a type of compression used to compress a payload of the compression block; and a content-addressable data structure builder to construct a content-addressable data structure based on the tokens and length values, the content-addressable data structure builder to write an entry in the content-addressable data structure comprising a length value and a count value, the count value indicating a number of times the length value was previously written to an entry in the content-addressable data structure.

Apparatus and method for efficient compression block decoding using content-addressable structure for header processing. For example, one embodiment of an apparatus comprises: a header parser to extract a sequence of tokens and corresponding length values from a header of a compression block, the tokens and corresponding length values associated with a type of compression used to compress a payload of the compression block; and a content-addressable data structure builder to construct a content-addressable data structure based on the tokens and length values, the content-addressable data structure builder to write an entry in the content-addressable data structure comprising a length value and a count value, the count value indicating a number of times the length value was previously written to an entry in the content-addressable data structure.

Techniques are disclosed relating to filtering access to a content-addressable memory (CAM). In some embodiments, a processor monitors for certain microarchitectural states and filters access to the CAM in states where there cannot be a match in the CAM or where matching entries will not be used even if there is a match. In some embodiments, toggle control circuitry prevents toggling of input lines when filtering CAM access, which may reduce dynamic power consumption. In some example embodiments, the CAM is used to access a load queue to validate that out-of-order execution for a set of instructions matches in-order execution, and situations where ordering should be checked are relatively rare.

A method for in memory computation of a neural network, the neural network having weights arranged in a matrix, includes previously storing the matrix in an associated memory device, receiving an input arranged in a vector and storing it in the memory device, and in-memory, computing an output of the network using the input and the weights.

A method for in memory computation of a neural network, the neural network having weights arranged in a matrix, includes previously storing the matrix in an associated memory device, receiving an input arranged in a vector and storing it in the memory device, and in-memory, computing an output of the network using the input and the weights.

The present disclosure discloses a ternary content addressable memory based on a memory diode, which includes a plurality of kernel units having functions of storing data, erasing/writing data, and comparing data; the kernel units are arranged in an array, all kernel units in a unit of row are connected to a same matching line, and all kernel units in a unit of column are connected to a same pair of complementary search signal lines; the kernel unit includes two memory diodes; top electrodes of a first memory diode and a second memory diode are respectively connected to a pair of complementary search signal lines, and bottom electrodes of the first memory diode and the second memory diode are connected to a same matching line. The present disclosure can greatly reduce a chip dimension of the ternary content addressable memory and reduce power consumption; the ternary content addressable memory of the present disclosure has a simple structure, which effectively simplifies a manufacturing process and reduces a manufacturing cost; the present disclosure provides and achieves a memory diode that is compatible with a standard CMOS process, which is suitable for currently rapidly developing semiconductor integrated circuits.

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.