Systems, methods, and apparatus including computer-readable mediums for managing block arrangement of super blocks in a memory such as NAND flash memory are provided. In one aspect, a memory controller for managing block arrangement of super blocks in a memory includes control circuitry coupled to the memory having at least two planes of physical blocks and configured to maintain block information of each individual physical block in the planes and select one or more physical blocks from the planes for a super block based on the block information of the physical blocks in the planes.

Systems, methods, and apparatus including computer-readable mediums for managing block arrangement of super blocks in a memory such as NAND flash memory are provided. In one aspect, a memory controller for managing block arrangement of super blocks in a memory includes control circuitry coupled to the memory having at least two planes of physical blocks and configured to maintain block information of each individual physical block in the planes and select one or more physical blocks from the planes for a super block based on the block information of the physical blocks in the planes.

A data processing system includes a memory device, a predetermined voltage generating circuit and a reference voltage generating circuit. The memory device stores system data and operates based on a system high voltage. The predetermined voltage generating circuit is coupled to the memory device and generates a predetermined voltage having a target voltage level according to a reference voltage. The target voltage level is the voltage level required for performing a write operation or an erase operation of the memory device. The reference voltage generating circuit generates the reference voltage. A voltage generator of the reference voltage generating circuit is enabled or disabled in response to a write protection signal, so as to selectively output the reference voltage. When the voltage generator is disabled, the reference voltage will not be output and the predetermined voltage having a target voltage level will accordingly not be generated.

Systems and methods for performing a pattern matching operation in a memory device are disclosed. The memory device may include a controller and memory arrays where the memory arrays store different patterns along bit lines. An input pattern is applied to the memory array(s) to determine whether the pattern is stored in the memory device. Word lines may be activated in series or in parallel to search for patterns within the memory array. The memory array may include memory cells that store binary digits, discrete values or analog values.

A semiconductor device is provided. The semiconductor device includes: a processor core which processes program data; a first memory mounted on the same semiconductor chip as the processor core; a second memory including an MRAM cell having a first MTJ (Magnetic Tunnel Junction) structure; a third memory including an MRAM cell having a second MTJ structure different from the first MTJ structure, wherein the processor core selectively stores the program data in one of the first memory, the second memory and the third memory, on the basis of an attribute of the program data.

An example semiconductor device includes: n conductive layers including first to n.sup.th conductive layers stacked in a first direction; a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type closer to the n.sup.th conductive layer than the first semiconductor region; a semiconductor layer provided between the first semiconductor region and the second semiconductor region, extending in the first direction, penetrating the n conductive layers, and having an impurity concentration lower than a first conductive impurity concentration of the first region and a second conductive impurity concentration of the second region; n charge storage regions including first to n.sup.th charge storage regions provided between the n conductive layers and the semiconductor layer, and a control circuit that controls a voltage applied to the n conductive layers to always prevent charges from being stored in at least one of the n charge storage regions.

A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit is mounted on the module board and coupled between a respective set of data signal lines and a respective set of memory devices. Each respective buffer circuit is configured to receive the module control signals and the module clock signal, and to buffer a respective set of data signals in response to the module control signals and the module clock signal. Each respective buffer circuit includes a delay circuit configured to delay the respective set of data signals by an amount determined based on at least one of the module control signals.

A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit is mounted on the module board and coupled between a respective set of data signal lines and a respective set of memory devices. Each respective buffer circuit is configured to receive the module control signals and the module clock signal, and to buffer a respective set of data signals in response to the module control signals and the module clock signal. Each respective buffer circuit includes a delay circuit configured to delay the respective set of data signals by an amount determined based on at least one of the module control signals.

A memory device and a method of operating the same. The memory device may include a memory block including a plurality of pages, and a control logic configured to include at least one register in which a plurality of program algorithms and a plurality of pieces of operation information are stored, select any one of the program algorithms in response to an address of a program target page, among the pages, and perform a program operation on the program target page based on the selected program algorithm and operation information corresponding to the selected program algorithm.

A memory device and a method of operating the same. The memory device may include a memory block including a plurality of pages, and a control logic configured to include at least one register in which a plurality of program algorithms and a plurality of pieces of operation information are stored, select any one of the program algorithms in response to an address of a program target page, among the pages, and perform a program operation on the program target page based on the selected program algorithm and operation information corresponding to the selected program algorithm.