The present inventions are related to systems and methods for accessing data from a flash memory, and more particularly to systems and methods for inter-cell interference handling in a flash memory. The systems and methods may include a soft information correction circuit that is operable to receive soft information corresponding to information accessed from a block of memory cells, and modify the soft information based upon a variance of the soft information and a median of the soft information to create corrected soft information, the corrected soft information being used to mitigate inter-cell interference in the block of memory cells.

A storage device and a data storing method thereof are provided. The storage device includes a data storage medium and the control unit. The data storage medium includes a data storage area with a plurality of first type of data blocks. When a data reading operation is executed on a current data block of the data storage medium, the control unit determines whether a read count of the current data block is greater than a first threshold, determines whether the current data block is one of the first type of data blocks and generate a determination result according to the result, the control unit selects a plurality of first type of data blocks and switches the selected data blocks to a fast mode. Finally, the control unit moves data stored in the current data block to the selected data blocks under fast mode.

Examples of a multi-level memory with direct access are described. Examples include designating an amount of a non-volatile random access memory (NVRAM) for use as memory for a computer system. Examples also include designating a second amount of the NVRAM to for use as storage for the computing device. Examples also include re-designating at least a first portion of the first amount of NVRAM from use as memory to use as storage.

Examples of a multi-level memory with direct access are described. Examples include designating an amount of a non-volatile random access memory (NVRAM) for use as memory for a computer system. Examples also include designating a second amount of the NVRAM to for use as storage for the computing device. Examples also include re-designating at least a first portion of the first amount of NVRAM from use as memory to use as storage.

A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array, a read only memory (ROM), a central processing unit, and a random access memory (RAM). The memory cell array stores data related to operating conditions of the semiconductor memory device. The ROM stores data used to control an operation of the semiconductor memory device. The central processing unit controls the operation of the semiconductor memory device according to the data read from the ROM. The central processing unit reads the data related to the operating conditions from the memory cell array in response to a requested operation and then temporarily stores the read data related to the operating conditions in the RAM. The central processing unit further reads the data related to the data related to the operating conditions from the RAM for controlling the operation of the semiconductor memory device.

A Solid-State Disk (SSD) Manufacturing Self Test (MST) capability enables an SSD manufacturer to generate and load tests onto SSDs, run the tests, and gather results. The SSDs self execute the loaded tests when powered up. The self executing is while coupled to a host that loaded the tests or while coupled to a rack unable to load the tests but enabled to provide power to the SSDs. The rack is optionally cost-reduced to enable cost-efficient parallel testing of relatively larger numbers of SSDs for production. The host writes the tests to an input SMART log of each SSD, and each SSD writes results to a respective included output SMART log. The commands include write drive, erase drive, SATA PHY burn-in, delay, and stress mode. The SSD MST capability is optionally used in conjunction with an SSD virtual manufacturing model.

Provided herein may be a memory device, a memory system having the memory device, and a method of operating the memory device. The memory device may include a memory cell array configured to store data, a peripheral circuit configured to perform a program operation on the memory cell array, and a control logic configured to perform the program operation by controlling the peripheral circuit and to perform a status check operation after the program operation. Here, the control logic may be configured to, based on a determination that the status check operation has passed, perform a number-of-program pulses comparison operation by comparing a number of program pulses used in the program operation to a first preset range.

According to one embodiment, there is provided a memory system including a nonvolatile semiconductor memory, a bus, and a controller. The nonvolatile semiconductor memory includes a first chip and a second chip. The bus is connected to the first chip and the second chip in common. The controller issues a first command to the first chip via the bus. The controller queues a second command whose access destination is identified to be the first chip at a first timing while the first chip is executing the first command. The controller issues to the second chip a third command whose access destination is identified to be the second chip after the first timing, via the bus in priority over the second command, while the first chip is executing the first command or after the execution of the first command finishes.

According to one embodiment, there is provided a memory system including a nonvolatile semiconductor memory, a bus, and a controller. The nonvolatile semiconductor memory includes a first chip and a second chip. The bus is connected to the first chip and the second chip in common. The controller issues a first command to the first chip via the bus. The controller queues a second command whose access destination is identified to be the first chip at a first timing while the first chip is executing the first command. The controller issues to the second chip a third command whose access destination is identified to be the second chip after the first timing, via the bus in priority over the second command, while the first chip is executing the first command or after the execution of the first command finishes.

According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.