In certain aspects, a memory device includes an array of memory cells including a plurality of rows of memory cells, a plurality of word lines respectively coupled to the plurality of rows of memory cells, and a peripheral circuit coupled to the plurality of word lines and configured to perform an erase operation on a selected row of memory cells of the plurality of rows of memory cells. The selected row of memory cells is coupled to a selected word line. To perform the erase operation, the peripheral circuit is configured to discharge an unselected word line coupled to an unselected row of memory cells of the plurality of rows of memory cells from an initial voltage to a discharge voltage in a first time period, and float the unselected word line in a second time period after the first time period.

Embodiments of three-dimensional memory device architectures and fabrication methods therefor are disclosed. In an example, the memory device includes a substrate and one or more peripheral devices on the substrate. The memory device also includes one or more interconnect layers and a semiconductor layer disposed over the one or more interconnect layers. A layer stack having alternating conductor and insulator layers is disposed above the semiconductor layer. A plurality of structures extend vertically through the layer stack. A first set of conductive lines are electrically coupled with a first set of the plurality of structures and a second set of conductive lines are electrically coupled with a second set of the plurality of structures different from the first set. The first and second sets of conductive lines are vertically distanced from opposite ends of the plurality of structures.

Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. The first transistor has a gate and is coupled between the data line and the first memory cell. The apparatus can include a second memory cell and a second select transistor having a gate. The apparatus can include a third select transistor having a gate. The second select transistor is coupled between the second memory cell and the third select transistor. The third select transistor is coupled between the second select transistor and a source. The apparatus can include a drive transistor coupled to both the gate of the first select transistor and the gate of the second select transistor or the gate of the third select transistor.

Techniques are described for optimizing the peak current during a program operation by controlling a timing and ramp rate of a program-inhibit voltage signal as a function of a program loop number and/or program progress. A transition voltage between a regulated ramp up rate and an unregulated ramp up rate can also be adjusted. For initial and final sets of program loops in a program operation, the ramp up of the program-inhibit voltage signal can occur early so that it overlaps with operations of sense circuits in updating their latches based on results from a verify test in a previous program loop. For an intermediate set of program loops, the overlap is avoided. The ramp up rate can be larger and the transition voltage smaller for the initial and final sets of program loops compared to the intermediate set of program loops.

A method of performing an erase operation on non-volatile storage is disclosed. The method comprises: applying, in a first erase loop of a plurality of erase loops of the erase operation, a first erase pulse to a first grouping of non-volatile storage elements; after applying the first erase pulse, determining an upper tail of a threshold voltage distribution of the first grouping of non-volatile storage elements; determining a difference between the upper tail of the first grouping of non-volatile storage elements and an upper tail of a threshold voltage distribution of a second grouping of non-volatile storage elements; and disabling, in a second erase loop of the plurality of erase loops, the erase operation on the first grouping of non-volatile storage elements if the difference is greater than or equal to the threshold amount.

A multi-bit level-shifter (MBLS) includes two or more input circuits correspondingly configured to operate in a first voltage domain. The MBLS also includes two or more single bit level shifters (SBLSs) electrically coupled correspondingly to the two or more input circuits, and correspondingly configured to operate in a second voltage domain. The MBLS also includes a control circuit configured to toggle each of the two or more SBLSs between a normal mode and a standby mode according to a toggle-control signal received from the control circuit.

A semiconductor memory device includes: a first wiring and a second wiring; a first selection transistor, a memory transistor, and a second selection transistor connected between the first wiring and the second wiring; and a third wiring and a fourth wiring connected to gate electrodes of the first selection transistor and the second selection transistor. From a first timing to a second timing, a first voltage that turns the first selection transistor ON is supplied to the third wiring, and a second voltage that turns the second selection transistor OFF is supplied to the fourth wiring. From the second timing to a third timing, a third voltage that turns the first selection transistor OFF is supplied to the third wiring, and at a fourth timing between the first timing and the third timing, at least one of a voltage and a current of the first wiring is detected.

A memory controller includes, in one embodiment, a memory interface and a controller circuit. The memory interface is configured to interface with a memory having a plurality of wordlines. The controller circuit is configured to program, with foggy-fine programming, a first portion of the plurality of wordlines to store first program data, program, with the foggy-fine programming, one or more wordlines of the plurality of wordlines in a non-fine state, the one or more wordlines neighboring the first portion, and program, with the foggy-fine programming, a second portion of the plurality of wordlines to store second program data, the second portion neighboring the one or more wordlines.

A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

A system and method for storing information in a quantum computer using a quantum storage ring. The method comprises cooling ions in the quantum storage ring to a low temperature; and binding the ions into a lattice structure, forming an ion Coulomb crystal.