A one-time programmable (OTP) memory cell is disclosed, which comprises an electric fuse structure, an anti-fuse transistor and a word select transistor. One end of the electric fuse structure is electrically connected to a gate of the anti-fuse transistor to form a first port of the OTP memory cell, the other end of the electric fuse structure is electrically connected to a source of the anti-fuse transistor and is connected to a drain of the word select transistor, and a gate and a source of the word select transistor form a second port and a third port of the OTP memory cell respectively. The operation method of the OTP memory cell has the capability of one-time correction, expanding the practicability of the OTP memory cell.

A structure includes a first data line and a first anti-fuse cell including first/second programming devices and first/second reading devices. The first programming device includes a first gate and first/second source/drain regions disposing on opposite sides of first gate. The second programming device includes a second gate separate from the first gate and coupled to a first word line and third/fourth source/drain regions disposing on opposite sides of second gate. The first reading device includes a third gate and fifth/sixth source/drain regions disposing on opposite sides of third gate. The second reading device includes a fourth gate and seventh/eighth source/drain regions disposing on opposite sides of fourth gate. The third/fourth gates are parts of the first continuous gate coupled to a second word line. The fifth/seventh source/drain regions are coupled to the second/fourth source/drain regions, respectively. The sixth/eighth source/drain regions are coupled to the first data line.

The present application provides a programmable memory device. The programmable memory device includes: an access transistor, comprising an active region formed in a substrate and a gate structure formed on the substrate, wherein the active region has a linear top view shape, the gate structure has a first portion and a second portion, the first portion is intersected with a section of the active region away from end portions of the active region, and the second portion is laterally spaced apart from the active region; and a capacitor, using a portion of the active region as a terminal, and further comprising an electrode and a dielectric layer, wherein the electrode is disposed on the portion of the active region and spaced apart from the gate structure, and at least a portion of the dielectric layer is sandwiched between the electrode and the portion of the active region.

A semiconductor memory device includes a command buffering unit suitable for receiving and buffering a command signal based on an enable control signal, a fuse array suitable for programming data based on the command signal, and an enable control unit suitable for generating the enable control signal, wherein an activation operation on the command buffering unit by the enable control signal is controlled during a programming operation period of the fuse array.

A device includes a first switch, a first irreversibly programmable memory point, and a second irreversibly programmable memory point coupled in parallel with the first irreversibly programmable memory point. The first switch and the parallel combination of the first and second irreversibly programmable memory points are coupled in series between a first node and a second node.

An OTP memory cell circuit includes a read access switch coupled to a fuse in a read current path to allow a read current to flow through the fuse during a read operation. The read access switch, which can be shut off in a write operation, is sized according to the read current to reduce leakage currents that can cause unreliable results. A diode circuit coupled to a node between the read access switch and the fuse provides a write current path through the fuse different from the read current path in the OTP memory cell circuit. The diode circuit is configured to drive, through the write current path including the fuse, a write current sufficient to blow the fuse in a write operation. The diode circuit occupies a smaller area than a write access transistor of comparable drive strength in the OTP memory cell circuit.

The present disclosure relates to a method for writing into a one-time programmable memory of an integrated circuit, the method comprising attempting, by a memory control circuit of the integrated circuit, to write data in at least one first register of the one-time programmable memory; verifying, by the memory control circuit, whether the data has been correctly written in the at least one first register; and, in case the data has not been correctly written in the at least one first register, attempting, by the memory control circuit, to write the data in at least one second register of the one-time programmable memory.

A small-area side-capacitor read-only memory device, a memory array and a method for operating the same are provided. The small-area side-capacitor read-only memory device embeds a field-effect transistor in a semiconductor substrate. The field-effect transistor includes a first dielectric layer and a first conductive gate stacked on the first dielectric layer. The side of the first conductive gate extends to the top of the second dielectric layer and connects to the second conductive gate to generate a capacitance effect. The second conductive gate has finger portions connected to a strip portion. Thus, the memory device employs the smallest layout area to generate the highest capacitance value, thereby decreasing the overall area of the read-only memory and performing efficient reading and writing.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.

Various one-time-programmable (OTP) memory cells are disclosed. An OTP memory cell includes an additional dopant region that extends at least partially under the gate of a transistor, such as an anti-fuse transistor. The additional dopant region provides an additional current path for a read current. Alternatively, an OTP memory cell includes three transistors; an anti-fuse transistor and two select transistors. The two select transistors can be configured as a cascaded select transistor or as two separate select transistors.