The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense line of an array, a first isolation device located between the first memory cell and first sensing circuitry corresponding thereto, and a second isolation device located between the first memory cell and second sensing circuitry corresponding to a second sense line. The first and the second isolation devices are operated to shift data in the array without transferring the data via an input/output line of the array.

The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense line of an array, a first isolation device located between the first memory cell and first sensing circuitry corresponding thereto, and a second isolation device located between the first memory cell and second sensing circuitry corresponding to a second sense line. The first and the second isolation devices are operated to shift data in the array without transferring the data via an input/output line of the array.

A multi-layer time-interleaving (TI) device and method of operation therefor. This device includes a plurality of TI layers configured to receive a plurality of input clock signals and to output a plurality of output clock signals, each of which can be configured to drive subsequent devices. The layers include at least a first and second layer including a fine-grain propagation device and a barrel-shifting propagation device configured to retime the plurality of input clock signals to produce divided output clock signals. The device can include additional barrel-shifting propagation devices to time interleave an initial two layers to produce one or more additional layers. Using negative phase stepping, the plurality of output clock signals is produced with optimal timing margin and synchronized on a single clock edge.

A semiconductor device and the like with low power consumption can be provided. A shift register in which a plurality of register circuits are connected to each other in series. The plurality of register circuits each include a flip-flop circuit. An operation of the flip-flop circuit of the register circuit in one stage is determined by a clock signal, an output signal of the register circuit in the previous stage, an output signal of the register circuit in the one stage, and an output signal of the register circuit in the next stage. Data stored in the flip-flop circuits in the register circuits in stages that are two or more stages before the one stage and in the register circuits in stages that are two or more stages after the one stage are not rewritten.

A register management system is coupled to a register. The register management system receives an address and functional data for a write operation to be performed on the register. The functional data includes write bits and mask bits associated with the write bits. One or more mask bits having a first logic state indicate that associated one or more write bits are to be written to the register, respectively. Based on the address, the register management system selects a first half of the register or a second half of the register to perform the write operation. Further, the register management system writes the one or more write bits associated with the one or more mask bits having the first logic state to one or more storage elements of the first half of the register or the second half of the register, respectively.

In some examples, an electronic device comprising an input ferroelectric (FE) capacitor, an output FE capacitor, and a channel positioned beneath the input FE capacitor and positioned beneath the output FE capacitor. In some examples, the channel is configured to carry a magnetic signal from the input FE capacitor to the output FE capacitor to cause a voltage change at the output FE capacitor. In some examples, the electronic device further comprises a transistor-based drive circuit electrically connected to an output node of the output FE capacitor. In some examples, the transistor-based drive circuit is configured to deliver, based on the voltage change at the output FE capacitor, an output signal to an input node of a second device.

Provided is a gate shift register including a plurality of stages receiving a plurality of clocks to generate gate output signals, in which an n-th stage of the stages dependently connected to each other includes an output node outputting an n-th gate output signal, a pull-up TFT switching a current flow between an input terminal of a clock having an n-th phase and the output node according to a potential of a Q node, a pull-down TFT switching the current flow between an input terminal of a low potential voltage and the output node according to a potential of a QB node, appnd a BTS compensation unit periodically discharging the QB node at a low potential level just after the n-th stage is reset and just until the n-th stage is set in a next frame.

The present disclosure relates to a gate driving circuit and a display device using the circuit. A gate driving circuit according to an aspect of the present disclosure comprises a Q node controller, a QB node controller, and an output unit generating a pulse-type output signal by controlling charging and discharging of an output terminal according to the voltages of the Q node and the QB node, and the QB node controller controls the voltage of the QB node in an alternating manner during a non-scan period in which the Q node controller outputs a low level voltage for the Q node.

A shift register circuit generates a clock enable signal in response to a start signal and in response to a clock signal. The shift register circuit generates multiple pulses in the clock enable signal in response to a single transition in the start signal and in response to control signals having values that indicate to generate more than one pulse in the clock enable signal. A multiplexer circuit provides an output signal for testing an electronic circuit based on an input signal or based on the clock signal in response to the clock enable signal.

A shift register circuit generates a clock enable signal in response to a start signal and in response to a clock signal. The shift register circuit generates multiple pulses in the clock enable signal in response to a single transition in the start signal and in response to control signals having values that indicate to generate more than one pulse in the clock enable signal. A multiplexer circuit provides an output signal for testing an electronic circuit based on an input signal or based on the clock signal in response to the clock enable signal.