Agate driving circuit and a display device are disclosed. The gate driving circuit includes a shift register including a plurality of stages. Among the stages, an Nth stage includes a first transistor charging a Q node and a junction stress control circuit. A pull-up transistor using the Q node as a gate input controls an output signal of a stage output terminal. The junction stress control circuit includes a first, second, and third control transistors. The first control transistor, the second control transistor, the third control transistor, and the first transistor are connected to each other through a common node. The second control transistor adjusts junction stresses for the first control transistor and the first transistor by controlling a voltage of the common node. When the second control transistor is turned off, the third control transistor discharges the voltage of the common node.

Agate driving circuit and a display device are disclosed. The gate driving circuit includes a shift register including a plurality of stages. Among the stages, an Nth stage includes a first transistor charging a Q node and a junction stress control circuit. A pull-up transistor using the Q node as a gate input controls an output signal of a stage output terminal. The junction stress control circuit includes a first, second, and third control transistors. The first control transistor, the second control transistor, the third control transistor, and the first transistor are connected to each other through a common node. The second control transistor adjusts junction stresses for the first control transistor and the first transistor by controlling a voltage of the common node. When the second control transistor is turned off, the third control transistor discharges the voltage of the common node.

A register file module comprising at least one register array comprising a plurality of latch devices is described. The plurality of latch devices is arranged to individually provide memory bit-cells when the register file module is configured to operate in a first, functional operating mode, and at least one clock control component is arranged to receive a clock signal and to propagate the clock signal to the latch devices within the at least one register array. The register file module is configurable to operate in a second, scan mode in which the latch devices within the at least one register array are arranged into at least one scan chain. The at least one clock control component is arranged to propagate the clock signal to the latch devices within the at least one register array such that alternate latch devices within the at least one scan chain receive an inverted form of the clock signal.

A register file module comprising at least one register array comprising a plurality of latch devices is described. The plurality of latch devices is arranged to individually provide memory bit-cells when the register file module is configured to operate in a first, functional operating mode, and at least one clock control component is arranged to receive a clock signal and to propagate the clock signal to the latch devices within the at least one register array. The register file module is configurable to operate in a second, scan mode in which the latch devices within the at least one register array are arranged into at least one scan chain. The at least one clock control component is arranged to propagate the clock signal to the latch devices within the at least one register array such that alternate latch devices within the at least one scan chain receive an inverted form of the clock signal.

A shift register and driving method thereof, and a gate driving circuit. The shift register of the present disclosure comprises: an input unit for controlling whether the signal of a first input end is inputted to a charging unit; a charging unit for charging a pull-up node; a pull-up unit for maintaining a high level of the pull-up node; a high level output unit for controlling whether the high level is outputted to the output end according to the level of the pull-up node; a pull-down unit for pulling down the level of the pull-up node and outputting the low level to the output end; a low level output unit for outputting the low level to the output end. The gate driving circuit of the present disclosure is formed by cascading a plurality of the above shift registers.

Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

A display driver is configured to drive a display device according to a video signal. The display signal includes a plurality of first to N-th output amplifiers (N is an integer greater than two) and an output electrical current capacity setting portion. The first to N-th output amplifiers are configured to amplify first to N-th gradation voltages a representing brightness level per pixel according to the video signal, so that the first to N-th output amplifiers obtain first to N-th pixel drive voltages. Further, the first to N-th output amplifiers are configured to output the first to N-th pixel drive voltages to the display device. The output electrical current capacity setting portion is configured to set an output electrical current capacity of each of the first to N-th output amplifiers individually or in a group of a plurality of output amplifiers.

A shift register, a method and a system for operating the shift register are provided. The shift register includes: an input circuit adapted to output a first voltage signal in response to an input signal; a trigger circuit adapted to generate a second voltage signal based on a first reference voltage and a second reference voltage, in response to the first voltage signal; and generate a third voltage signal, different than the second voltage signal, based on the first reference voltage and the second reference voltage, in response to the first voltage signal; and an output circuit adapted to output a scanning signal based on the second voltage signal and the third voltage signal. The voltages of the second voltage signal and the third voltage signal depend on a voltage dividing value of the trigger circuit, and the voltage dividing value of the trigger circuit is based on the first reference voltage and the second reference voltage.

A current corresponding to the difference between an input signal voltage and an output signal voltage is generated as an amplification acceleration current. The amplification acceleration current is sent to an output node of a current mirror, which drives a transistor in an output amplifier stage, and therefore added to a current to drive the transistor in the output amplifier stage.