The present disclosure provides an innovative circuit structure for control insertion into a multiple-word wide data stream. The control-insertion circuit structure is advantageously scalable as the data width increases. An exemplary implementation of the control-insertion circuit structure includes a multiple-layer shifting circuit. The multiple-layer shifting circuit has some similarities with a barrel shifter. However, unlike a barrel shifter, the multiple-layer shifting circuit moves data words in both directions and moves portions of the data to create spaces or holes in the data (rather than moving the entire width as a barrel shifter does). The output of the multiple-layer shifting circuit is a swiss-cheese-like structure of data, where the spaces or holes in the data are available for control insertion. Other features, aspects and embodiments are also disclosed.

In a method of adaptive buffering in a mobile device having a host processor and a sensor processor coupled with the host processor, the sensor processor is used to buffer data received from a sensor that is operated by the sensor processor. The data is buffered by the sensor processor into a circular data buffer. Responsive to the sensor processor detecting triggering data within the received data: a first adaptive data buffering action is initiated with respect to the data received from the sensor operated by the sensor processor; a second adaptive data buffering action is initiated with respect to second data received from a second sensor of the mobile device; and a command is sent from the sensor processor to a second processor.

In a method of adaptive buffering in a mobile device having a host processor and a sensor processor coupled with the host processor, the sensor processor is used to buffer data received from a sensor that is operated by the sensor processor. The data is buffered by the sensor processor into a circular data buffer. Responsive to the sensor processor detecting triggering data within the received data: a first adaptive data buffering action is initiated with respect to the data received from the sensor operated by the sensor processor; a second adaptive data buffering action is initiated with respect to second data received from a second sensor of the mobile device; and a command is sent from the sensor processor to a second processor.

A modular system including a set of functionality tiles and a control tile storing a storage structure, an initialization file, and operation instructions. The method for operating a custom device made using the modular system includes: sending operation settings for each tile to the respective tile upon device initialization; operating each tile based on the operation settings; writing the output from each tile to the storage structure; monitoring data streams within the storage structure for a trigger event; reading data off the storage structure in response to occurrence of the trigger event; and processing the read data according to a processing function specified by the operation instructions.

A modular system including a set of functionality tiles and a control tile storing a storage structure, an initialization file, and operation instructions. The method for operating a custom device made using the modular system includes: sending operation settings for each tile to the respective tile upon device initialization; operating each tile based on the operation settings; writing the output from each tile to the storage structure; monitoring data streams within the storage structure for a trigger event; reading data off the storage structure in response to occurrence of the trigger event; and processing the read data according to a processing function specified by the operation instructions.

An interconnect system includes host devices, one or more memory devices, and a routing system to connect the host devices and the one or more memory devices. Respective ones of the host devices include an interface to communicate packet requests over respective packetized links. Respective ones of the one or more memory devices include an interface to receive and respond to the packet requests over the respective packetized links. The routing system includes devices interconnected in a routing topology. Respective ones of the devices include a switch and interfaces. The routing system is to route the packet requests and responses between the host devices and respective memory device destinations over the respective packetized links.

An interconnect system includes host devices, one or more memory devices, and a routing system to connect the host devices and the one or more memory devices. Respective ones of the host devices include an interface to communicate packet requests over respective packetized links. Respective ones of the one or more memory devices include an interface to receive and respond to the packet requests over the respective packetized links. The routing system includes devices interconnected in a routing topology. Respective ones of the devices include a switch and interfaces. The routing system is to route the packet requests and responses between the host devices and respective memory device destinations over the respective packetized links.

A measurement system is provided that performs a qualified store algorithm. When performing the algorithm, the measurement system stores in memory digital data samples acquired during a time window while a qualification signal is valid, a preselected number of digital data samples acquired prior to and adjacent in time to the time window, and a preselected number of digital data samples acquired subsequent to and adjacent in time to the time window.

A measurement system is provided that performs a qualified store algorithm. When performing the algorithm, the measurement system stores in memory digital data samples acquired during a time window while a qualification signal is valid, a preselected number of digital data samples acquired prior to and adjacent in time to the time window, and a preselected number of digital data samples acquired subsequent to and adjacent in time to the time window.

A system and method for managing data in a ring buffer is disclosed. The system includes a legacy ring buffer functioning as an on-chip ring buffer, a supplemental buffer for storing data in the ring buffer, a preload ring buffer that is on-chip and capable of receiving preload data from the supplemental buffer, a write controller that determines where to write data that is write requested by a write client of the ring buffer, and a read controller that controls a return of data to a read client pursuant to a read request to the ring buffer.