A system and method for managing data in a ring buffer is disclosed. The system includes a legacy ring buffer functioning as an on-chip ring buffer, a supplemental buffer for storing data in the ring buffer, a preload ring buffer that is on-chip and capable of receiving preload data from the supplemental buffer, a write controller that determines where to write data that is write requested by a write client of the ring buffer, and a read controller that controls a return of data to a read client pursuant to a read request to the ring buffer.

A system and method for managing data in a ring buffer is disclosed. The system includes a legacy ring buffer functioning as an on-chip ring buffer, a supplemental buffer for storing data in the ring buffer, a preload ring buffer that is on-chip and capable of receiving preload data from the supplemental buffer, a write controller that determines where to write data that is write requested by a write client of the ring buffer, and a read controller that controls a return of data to a read client pursuant to a read request to the ring buffer.

Methods and systems which involve computer memories are disclosed herein. The methods and systems involve integrated Random Access Memory (RAM) using loops of inverters. A disclosed RAM comprises a set of loops of inverters. The loops of inverters in the set of loops of inverters are addressable using a set of corresponding addresses. The RAM further comprises a write circuit configured to write a value to a first loop of inverters when provided with a corresponding address for the first loop of inverters. The first loop of inverters is in the set of loops of inverters and the corresponding address is in the set of corresponding addresses. The RAM further comprises a read circuit configured to read the value from the first loop of inverters when provided with the corresponding address.

Methods and systems which involve computer memories are disclosed herein. The methods and systems involve integrated Random Access Memory (RAM) using loops of inverters. A disclosed RAM comprises a set of loops of inverters. The loops of inverters in the set of loops of inverters are addressable using a set of corresponding addresses. The RAM further comprises a write circuit configured to write a value to a first loop of inverters when provided with a corresponding address for the first loop of inverters. The first loop of inverters is in the set of loops of inverters and the corresponding address is in the set of corresponding addresses. The RAM further comprises a read circuit configured to read the value from the first loop of inverters when provided with the corresponding address.

A comparator circuit includes a first transistor, a second transistor, a load circuit, a first adjustment circuit and a second adjustment circuit. A terminal of the first transistor is coupled to a first node, another terminal of the first transistor is coupled to a first control node, and a gate of the first transistor is configured to receive a first control signal. A terminal of the second transistor is coupled to the first node, another terminal of the second transistor is coupled to a second control node, and a gate of the second transistor is configured to receive a second control signal. A terminal of the load circuit is coupled to a second node, and another terminal of the load circuit is coupled to the first control node and the second control node.

Delay line memory device, systems and methods are disclosed. In one aspect, a delay line memory device includes a substrate; an electronic unit disposed on the substrate and operable to receive, amplify, and/or synchronize data signals into a bit stream to be transmitted as acoustic pulses carrying data stored in the delay line memory device; a first and a second piezoelectric transducer disposed on the substrate and in communication with the electronic unit, in which the first piezoelectric transducer is operable to transmit the data signals to the acoustic pulses that carry the data through the bulk of the substrate, and the second piezoelectric transducer is operable to transduce the received acoustic pulses to intermediate electrical signals containing the data, which are transferred to the electronic unit via an electrical interconnect to cause refresh of the data in the delay line memory device.

Optical networks may store information or data therein by maintaining the information or data in motion. The optical networks may include optical fiber rings configured to receive optical signals comprising the information or data and to circulate the optical signals within the optical fiber rings. The optical signals and the information or data may be transferred out of the optical fiber rings in order to amplify the optical signals (e.g., to overcome losses due to attenuation within the optical fiber rings), to analyze the optical signals according to one or more processing techniques, or to transfer the information or data to another computer device upon request. If continued storage of the information or data is required, an optical signal including the information or data may be transferred back into the optical fiber rings and may continue to circulate therein.

Provided is an information processing device configured to: acquire blocks, each of the blocks being a part of an array; generate a total sum block, a maximum block, a first maximum block, and a last maximum block for a plurality of sub-blocks; iteratively execute processing of calculating, for a new sub-block, a new total sum block, a new maximum block, a new first maximum block, and a new last maximum block; determine, after the processing is executed a predetermined number of times, a total sum of element values, a maximum value of subset sums, a maximum value of subset sums summed from a first element, and a maximum value of subset sums summed to a last element for each of the blocks; and calculate the maximum value of subset sums in the array based on the determined values.

A modular system including a set of functionality tiles and a control tile storing a storage structure, an initialization file, and operation instructions. The method for operating a custom device made using the modular system includes: sending operation settings for each tile to the respective tile upon device initialization; operating each tile based on the operation settings; writing the output from each tile to the storage structure; monitoring data streams within the storage structure for a trigger event; reading data off the storage structure in response to occurrence of the trigger event; and processing the read data according to a processing function specified by the operation instructions.

A modular system including a set of functionality tiles and a control tile storing a storage structure, an initialization file, and operation instructions. The method for operating a custom device made using the modular system includes: sending operation settings for each tile to the respective tile upon device initialization; operating each tile based on the operation settings; writing the output from each tile to the storage structure; monitoring data streams within the storage structure for a trigger event; reading data off the storage structure in response to occurrence of the trigger event; and processing the read data according to a processing function specified by the operation instructions.