To provide a semiconductor device with a novel structure. The semiconductor device includes a plurality of constant current circuits each given a digital signal. The constant current circuits each include a first transistor to a third transistor. The first transistor has a function of making a first current corresponding to set analog potential flow therethrough. The second transistor has a function of controlling the first current flowing between a source and a drain of the first transistor, in response to the digital signal. The third transistor has a function of holding the analog potential supplied to a gate of the first transistor, by being turned off. The first transistor to the third transistor each include a semiconductor layer including an oxide semiconductor in a channel formation region.

According to an example, discrete-time analog filtering may include receiving an input signal, and sampling the input signal to determine sampled input signal values related to the input signal.

A magnetic memory device includes a first magnetic memory device, a second magnetic memory device, a pulse power supplying current pulses to the first and second magnetic memory devices; and a switch configured to selectively connect the pulse power to one of the first and second magnetic memory devices. A resistance value of an MTJ device composed of the first fixed layer, the first non-magnetic layer, and the free layer is different from a resistance value of a MTJ device composed of the second fixed layer, the second non-magnetic layer, and the free layer.

Methods, systems, and devices for mimicking neuro-biological architectures that may be present in a nervous system are described herein. A memory device may include a memory unit configured to store a value. A memory unit may include a first memory cell (e.g., an aggressor memory cell) and a plurality of other memory cells (e.g., victim memory cells). The memory unit may use thermal disturbances of the victim memory cells that may be based on an access operation to store the analog value. Thermal energy output by the aggressor memory cell during an access operation (e.g., a write operation) may cause the state of the victim memory cells to alter based on thermal relationship between the aggressor memory cell and at least some of the victim memory cells. The memory unit may be read by detecting and combining the weights of the victim memory cells during a read operation.

The present disclosure describes analog memories for use in a computer, such as a computer using a combination of analog and digital components/elements used in a cohesive manner.

An embodiment in the application may include an analog memory structure, and methods of writing to such a structure, including a volatile memory element in series with a non-volatile memory element. The analog memory structure may change resistance upon application of a voltage. This may enable accelerated writing of the analog memory structure.

Techniques are provided for programming a multi-level self-selecting memory cell that includes a chalcogenide material. To program one or more intermediate memory states to the self-selecting memory cell, a programming pulse sequence that includes two pulses may be used. A first pulse of the programming pulse sequence may have a first polarity and a first magnitude and the second pulse of the programming pulse sequence may have a second polarity different than the first polarity and a second magnitude different than the first magnitude. After applying both pulses in the programming pulse sequence, the self-selecting memory cell may store an intermediate state that represents two bits of data (e.g., a logic ‘01’ or a logic ‘10’).

An analog content addressable memory (aCAM) that enables parallel searching of analog ranges of values and generates analog outputs that quantify matches between input data and stored data is disclosed. The input data can be compared with the stored data, and the input data can be determined to match the stored data based on a value associated with the input data being within a range associated with the stored data. The aCAM can generate an analog output that represents a number of matches and a number of mismatches between the input data and the stored data. Based on the analog output, whether the input data matches the stored data and a degree to which the input data matches the stored data can be determined.

An analog delay line includes a clock generator, an analog sampling circuit, a bank of analog memory cells, a memory controller, an analog readout circuit, and an analog multiplexer. The clock generator is configured to output plural reception clock signals of different frequencies and plural transmission clock signals of different frequencies, the transmission clock signals offset in accumulated phase relative to the reception clock signals. The analog sampling circuit is controlled by at least one of the reception clock signals, and is configured to output a sequence of sampled voltages of an analog input signal. The memory controller is configured to control a write operation at a write frequency of at least one of the reception clock signals and a read operation at a read frequency of at least one of the transmission clock signals. The write operation is for sequentially storing the sampled voltages received from the analog sampling circuit in the bank of analog memory cells, and the read operation is for sequentially reading the sampled voltages from the bank of analog memory cells. The analog readout circuit is configured to buffer the sampled voltages read from the bank of analog memory cells. The analog multiplexer is controlled by at least one of the transmission clock signals, and is configured to multiplex the sampled voltages buffered by the readout circuit to generate an analog output signal. A sampling rate of the analog input signal is within a factor of 2 of a sampling rate of the analog output signal.

An analog delay line includes a clock generator, an analog sampling circuit, a bank of analog memory cells, a memory controller, an analog readout circuit, and an analog multiplexer. The clock generator is configured to output plural reception clock signals of different frequencies and plural transmission clock signals of different frequencies, the transmission clock signals offset in accumulated phase relative to the reception clock signals. The analog sampling circuit is controlled by at least one of the reception clock signals, and is configured to output a sequence of sampled voltages of an analog input signal. The memory controller is configured to control a write operation at a write frequency of at least one of the reception clock signals and a read operation at a read frequency of at least one of the transmission clock signals. The write operation is for sequentially storing the sampled voltages received from the analog sampling circuit in the bank of analog memory cells, and the read operation is for sequentially reading the sampled voltages from the bank of analog memory cells. The analog readout circuit is configured to buffer the sampled voltages read from the bank of analog memory cells. The analog multiplexer is controlled by at least one of the transmission clock signals, and is configured to multiplex the sampled voltages buffered by the readout circuit to generate an analog output signal. A sampling rate of the analog input signal is within a factor of 2 of a sampling rate of the analog output signal.