A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.

An example apparatus includes a memory comprising a plurality of managed units corresponding to respective groups of resistance variable memory cells and a controller coupled to the memory. The controller is configured to cause performance of a cleaning operation on a selected group of the memory cells and generation of error correction code (ECC) parity data. The controller may be further configured to cause performance of a write operation on the selected group of cells to write an inverted state of at least one data value to the selected group of cells and write an inverted state of at least one of the ECC parity data to the selected group of cells.

A three-dimensional stacked integrated circuit (3D SIC) that can have at least a first 3D XPoint (3DXP) die and, in some examples, can have at least a second 3DXP die too. In such examples, the first 3DXP die and the second 3DXP die can be stacked. The 3D SIC can be partitioned into a plurality of columns that are perpendicular to each of the stacked dies. In such examples, when a first column of the plurality of columns is determined as failing, data stored in the first column can be replicated to a second column of the plurality of columns. Also, for example, when a part of a first column of the plurality of columns is determined as failing, data stored in the part of the first column can be replicated to a corresponding part of a second column of the plurality of columns.

Methods, systems, and devices for adjustable column address scramble using fuses are described. A testing device may detect a first error in a first column plane of a memory array and a second error in a second column plane of the memory array. The testing device may identify a first column address of the first column plane associated with the first error and a second column address of the second column plane based on detecting the first error and the second error. The testing device may determine, for the first column plane, a configuration for scrambling column addresses of the first column plane to different column addresses of the first column plane. In some cases, the testing device may perform a fuse blow of a fuse associated with the first column plane to implement the determined configuration.

A storage device having improved data recovery performance includes a memory device including a first storage region and a second storage region, and a memory controller that controls the memory device. Before performing a write operation in the first storage region, the memory controller may backup data previously stored in the first storage region, based on a fail probability of the write operation to be performed in the first storage region. If the write operation fails, the previously-stored data may be recovered from where it was backed up.

A system includes a memory device including a first unit, and a processing device, operatively coupled to the memory device, to perform operations including identifying a set of parity data on a volatile memory, determining whether the set of parity data satisfies a condition pertaining to a size of the set of parity data, and responsive to determining that the set of parity data does not satisfy the condition, appending parity data to the set of parity data. The parity data is generated based on a set of host data written on the first unit.

A method for accessing a memory module includes; encoding first data of a first partial burst length to generate first parities and first cyclic redundancy codes, encoding second data of a second partial burst length to generate second parities and second cyclic redundancy codes, writing the first data and the second data to first memory devices, and writing the first parities, the first cyclic redundancy codes, the second parities, and the second cyclic redundancy codes to a second memory device and a third memory device.

Disclosed is a method for grading memory modules comprising: a testing step which applies at least one test procedure to test a memory, each test procedure is provided with a reliability test; and a grading step which grades the memory into corresponding grade level according to test results of said at least one test procedure, and each test result includes a reliability test result wherein the reliability test has the following steps in sequence: performing a data-writing operation on the memory, wherein the data-writing operation is an operation that writes data to the memory; stopping electric charging the memory; halting a predetermined time period; electric charging the memory; checking data integrity of the memory; and generating the reliability test result according to the data integrity.

A memory system includes a non-volatile memory and a memory controller. The non-volatile memory includes a memory cell array having pages. The memory system is configured to execute a first operation method and a second operation method. The memory system includes a control information storage unit in which a first value is set for pages having a write operation speed that is slower than a first speed, and a second value is set for pages having a write operation speed that is equal to or higher than the first speed. The memory system is configured to, at the time of write operation, select the first operation method for a target page having the first value and perform the write operation using the first operation method, and select the second operation method for a target page having the second value and perform the write operation using the second operation method.

Disclosed is a computer-implemented method for optimizing read thresholds of a memory device using a deep neural network engine, comprising reading, using a set of read threshold voltages applied to the memory device, data from the memory device under a first set of operating conditions that contribute to read errors in the memory device, producing a labeled training data set using the set of read threshold voltages under the first set of the operating conditions, determining, based on characteristics of the memory device, a number of layers, a size of each layer, and a number of input and output nodes of the deep neural network engine, training the deep neural network engine using the labeled training data set, and using the trained deep neural network engine to compute read thresholds voltage values under a second set of operating conditions.