Exemplary methods, apparatuses, and systems include determining that data in a group of memory cells of a first memory device is to be moved to a spare group of memory cells. The group of memory cells spans a first dimension and a second dimension that is orthogonal to the first dimension and the spare group of memory cells also spans the first dimension and the second dimension. The data is read from the group of memory cells along the first dimension of the group of memory cells. The data is written to the spare group of memory cells along the second dimension of the spare group of memory cells.

A memory system including a first central processing unit, a first memory module connected to the first central processing unit by a first channel, a second memory module connected to the first central processing unit by a second channel, and a third memory module connected to the first central processing unit by a third channel may be provided. Each of the first memory module, the second memory module, and the third memory module may be configured to write the same data in a data area thereof and a mirroring data area thereof in response to an address in a mirroring mode.

A health check manager may detect a trigger for a capacitor health check for a memory sub-system. The health check manager may determine a number of write commands in a set of one or more pending commands for a memory die of the memory sub-system and set a start time for the capacitor health check based on the number of write commands in the set of one or more pending commands. In some cases, the health check manager may perform the capacitor health check in accordance with the start time.

A semiconductor device includes a memory bank including a first memory block, a second memory block, and a redundancy memory block, and a column line selection circuit configured, when a fail occurs in a first column line of the first memory block, to replace the first column line of the first memory block with a first redundancy line of the redundancy memory block, and replace a second column line of the second memory block with a second redundancy line of the redundancy memory block.

Various implementations described herein are directed to a device having memory architecture with an array of memory cells arranged in multiple columns with redundancy including first columns of memory cells disposed in a first region along with second columns of memory cells and redundancy columns of memory cells disposed in a second region that is laterally opposite the first region. The device may have column shifting logic that is configured to receive data from the multiple columns, shift the data from the first columns in the first region to a first set of the redundancy columns in the second region, and shift data from the second columns in the second region to a second set of the redundancy columns in the second region.

A memory includes: a memory array; a nonvolatile memory circuit suitable for storing a plurality of data sets each including flag information and multi-bit data; a plurality of repair register sets suitable for receiving and storing the multi-bit data included in the data sets whose flag information is marked for repair among the data sets during a boot-up operation; a plurality of setting register sets suitable for storing setting information included in the data sets whose flag information is marked for setting among the data sets during the boot-up operation; and a repair circuit suitable for repairing a defect in the memory array based on the multi-bit data stored in the repair register sets.

A method includes identifying an independent data object of a plurality of independent data objects for retrieval from dispersed storage network (DSN) memory. The method further includes determining a mapping of the plurality of independent data objects into a data matrix, wherein the mapping is in accordance with the dispersed storage error encoding function. The method further includes identifying, based on the mapping, an encoded data slice of the set of encoded data slices corresponding to the independent data object. The method further includes sending a retrieval request to a storage unit of the DSN memory regarding the encoded data slice. When the encoded data slice is received, the method further includes decoding the encoding data slice in accordance with the dispersed storage error encoding function and the mapping to reproduce the independent data object.

A method for operating a memory includes determining to perform an error correction operation; determining whether to perform an error correction operation; generating an internal address when the error correction operation is performed; reading data from memory cells that are selected based on the internal address and an error correction code corresponding to the data; performing an error correction operation on the data based on the error correction code to produce an error-corrected data; writing the error-corrected data and an error correction code corresponding to the error-corrected data into the memory cells; determining one or more regions among regions in the memory as a repair-requiring region based on an error detected when the error correction operation is performed; receiving a first command; backing up the data and the error correction code into a redundant region in response to the first command; and repairing the repair-requiring region with the redundant region.

A synergistic approach to mitigating crosstalk in a Dynamic Random-Access Memory (DRAM) implements the use of a random number generator to increment a counter in a probabilistic manner. The counter is formed by reclaiming bytes of a double data rate (DDR) fault isolation feature. The random number generator value may be compared against a predetermined parameter value and a determination may be made whether or not to extract and increment the counter based on a result of the comparison. A logic controller compares the counter value to a predetermined hotness threshold parameter and a flag is set based on an existence of an address match in local memory. Based on the results of the comparison, access to the DRAM is reduced.

Embodiments of the disclosure are drawn to apparatuses and methods for automatic soft post-package repair (ASPPR). A memory may receive a row address along with a signal indicating an ASPPR operation, such as a bad page flag being set. A word line engine generates a physical address based on the row address, and ASPPR registers stores the physical address. The time it takes from receiving the row address to storing the physical address may be within the timing of an access operation on the memory such as tRAS. The row address may specify a single page of information. If the bad page flag is set, then a subsequent PPR operation may blow fuses to encode the physical address stored in the ASPPR registers.