A memory system includes a memory medium and a memory controller. The memory medium has a second address system that is different from a first address system of a host. The memory controller performs a control operation to access the memory medium based on a command from the host. The memory controller is configured to store a second address, corresponding to an address of a read data, when an error of the read data that is outputted from the memory medium is uncorrectable and is configured to repair a region of the memory medium, designated by the second address, when the region of the memory medium that is designated by the second address is repairable.

Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. Initial pages of multiple bit per cell data are encoded to obtain at least first and second pages of single bit per cell data. The initial pages of multiple bit per cell data are programmed into a primary set of memory cells, while concurrently the first and second pages of single bit per cell data are programmed into first and second backup sets of memory cells, respectively. In the event of a power loss, the first and second pages of single bit per cell data are read from the first and second backup sets of memory cells, and decoded to recover the initial pages of multiple bit per cell data.

A semiconductor device includes a memory bank including a first memory block, a second memory block, and a redundancy memory block, and a column line selection circuit configured, when a fail occurs in a first column line of the first memory block, to replace the first column line of the first memory block with a first redundancy line of the redundancy memory block, and replace a second column line of the second memory block with a second redundancy line of the redundancy memory block.

A memory circuit includes a first memory array and a second memory array. The first memory array and the second memory array are independent. The first memory array includes a plurality of general bits and the second memory array includes a plurality of spare bits. An address of defective bit in the first memory array is stored in the second memory array, and the memory circuit repairs the defective bit by one of the spare bits according to the address.

An apparatus includes one or more control circuits configured to connect to a plurality of non-volatile memory cells arranged along word lines. The one or more control circuits are configured to receive a plurality of encoded portions of data to be programmed in non-volatile memory cells of a target word line, each encoded portion of data encoded according to an Error Correction Code (ECC) encoding scheme, and arrange the plurality of encoded portions of data in a plurality of rows of data latches corresponding to a plurality of logical pages such that each encoded portion of data is distributed across two or more rows of data latches. The one or more control circuits are also configured to program the distributed encoded portions of data from the plurality of rows of data latches into non-volatile memory cells along a target word line.

According to one embodiment, there is provided a memory system including a non-volatile memory, and a controller. The controller selects one read method from a plurality of read methods with different time required to perform a read operation on the non-volatile memory and issues a first read command according to the selected one read method to the non-volatile memory.

A memory device includes a row decoder, a column decoder, and a repair control circuit, which is configured to: (i) compare a row address with a stored failed row address, (ii) compare a column address with a stored failed column address, (iii) control the row decoder to activate the at least one of a plurality of redundancy word lines when the row address corresponds to the failed row address, and (iv) control the column decoder to activate at least one of a plurality of redundancy bit lines when the column address corresponds to the failed column address. The repair control circuit varies a repair unit according to an address input during a repair operation.

Methods, systems, and devices for adjustable programming pulses for a multi-level cell are described. A memory device may modify a characteristic of a programming pulse for an intermediate logic state based on a metric of reliability of associated memory cells. The modified characteristic may increase a read window and reverse a movement of a shifted threshold voltage distribution (e.g., by moving the threshold voltage distribution farther from one or more other voltage distributions). The metric of reliability may be determined by performing test writes may be a quantity of cycles of use for the memory cells, a bit error rate, and/or a quantity of reads of the first state. The information associated with the modified second pulse may be stored in fuses or memory cells, or may be implemented by a memory device controller or circuitry of the memory device.

The disclosed technology provides for automatically skipping bad block(s) in continuous read or sequential read operations in memory devices including NAND flash memory. Bad blocks can be skipped by analyzing block integrity during one at a time addressing of the blocks, or by skipping sets of consecutive bad blocks in a set of bad blocks using stored bad block information. Multiple sets of consecutive bad blocks can also be analyzed and skipped. A list of good blocks can be maintained, and only good blocks are used when performing a continuous cache read or sequential read operation. The list can be maintained in non-volatile memory enabling the device to load the block addresses upon power on startup. Additionally, a command to add additional blocks when received can implement adding new blocks to the list.

A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.