A class D amplification circuit includes a low-pass filter circuit including an inductor, first and second capacitors, an input terminal, a first potential terminal, a second potential terminal, and an output terminal. The input terminal is connected to a drive circuit. The first potential terminal is connected to a first potential. The second potential terminal is connected to a second potential that is lower than the first potential. The output terminal is connected to a load circuit. One external electrode of the first capacitor is connected to the first potential terminal. One external electrode of the second capacitor is connected to the second potential terminal. Another external electrode of the first capacitor and another external electrode of the second capacitor are connected to the output terminal. One external electrode of the inductor is connected to the input terminal. Another external electrode of the inductor is connected to the output terminal.

Methods and apparatuses for use in tuning reactance are described. Open loop and closed loop control for tuning of reactances are also described. Tunable inductors and/or tunable capacitors may be used in filters, resonant circuits, matching networks, and phase shifters. Ability to control inductance and/or capacitance in a circuit leads to flexibility in operation of the circuit, since the circuit may be tuned to operate under a range of different operating frequencies.

Methods and apparatuses for use in tuning reactance are described. Open loop and closed loop control for tuning of reactances are also described. Tunable inductors and/or tunable capacitors may be used in filters, resonant circuits, matching networks, and phase shifters. Ability to control inductance and/or capacitance in a circuit leads to flexibility in operation of the circuit, since the circuit may be tuned to operate under a range of different operating frequencies.

An imaging system includes an array of photodetectors and electronic circuitry associated with the photodetectors to read intensity values from the photodetectors. The electronic circuitry can include an integrator with an integrator capacitor having a nominal capacitance, wherein a gain of the electronic circuitry associated with a photodetector can depend at least in part on the actual capacitance of the integrator capacitor, the actual capacitance differing from the nominal capacitance. The imaging system can be configured to determine a gain factor that depends at least in part on the actual capacitance and/or a signal voltage input to the integrator. The imaging system can be configured to apply the gain factor based at least in part on the actual capacitance of the integrator capacitor calculated. The imaging system can be a thermal imaging system and may include an infrared camera core.

An imaging system includes an array of photodetectors and electronic circuitry associated with the photodetectors to read intensity values from the photodetectors. The electronic circuitry can include an integrator with an integrator capacitor having a nominal capacitance, wherein a gain of the electronic circuitry associated with a photodetector can depend at least in part on the actual capacitance of the integrator capacitor, the actual capacitance differing from the nominal capacitance. The imaging system can be configured to determine a gain factor that depends at least in part on the actual capacitance and/or a signal voltage input to the integrator. The imaging system can be configured to apply the gain factor based at least in part on the actual capacitance of the integrator capacitor calculated. The imaging system can be a thermal imaging system and may include an infrared camera core.

An apparatus and associated method are provided involving one or more registers configured to store a plurality of values including a first value corresponding with a first capacitance, and a second value corresponding with a second capacitance. Further included is a decoder configured to decode the values into corresponding capacitive settings. Also included is one or more capacitive elements in electrical communication with the decoder. Such one or more capacitive elements are configured to exhibit different capacitances, based on the capacitive settings. Also included is control circuitry in electrical communication with the decoder and the one or more registers. Such control circuitry is configured to control a transition of the capacitance of the one or more capacitive elements from the first capacitance to the second capacitance, by creating a plurality of additional values between the first value and the second value for being decoded by the decoder.

An apparatus and associated method are provided involving one or more registers configured to store a plurality of values including a first value corresponding with a first capacitance, and a second value corresponding with a second capacitance. Further included is a decoder configured to decode the values into corresponding capacitive settings. Also included is one or more capacitive elements in electrical communication with the decoder. Such one or more capacitive elements are configured to exhibit different capacitances, based on the capacitive settings. Also included is control circuitry in electrical communication with the decoder and the one or more registers. Such control circuitry is configured to control a transition of the capacitance of the one or more capacitive elements from the first capacitance to the second capacitance, by creating a plurality of additional values between the first value and the second value for being decoded by the decoder.

The present subject matter relates to devices, systems, and methods for controlling an array of two-state elements that can be independently positioned in either first state or a second state. A non-volatile memory in communication with the plurality of two-state elements is configured to receive an input digital control word that addresses a location within the non-volatile memory and to output one of a plurality of array control words stored at the location addressed within the memory to the plurality of two-state elements, wherein the array control word sets a predetermined combination of the plurality of two-state elements to be in the first state and in the second state, and wherein the predetermined combination of the plurality of two-state elements in the first state and in the second state optimally achieves a desired behavior of the array corresponding to the input digital control word.

A Process Compensated Delay has been disclosed. In one implementation delay is primarily based on electron mobility.

A Process Compensated Delay has been disclosed. In one implementation delay is primarily based on electron mobility.