In one embodiment, an RF impedance matching circuit is disclosed. The matching circuit is coupled between a plasma chamber and an RF source providing an RF signal having a frequency. The matching circuit includes a first electronically variable capacitor having a first variable capacitance and a second electronically variable capacitor having a second variable capacitance. A control circuit determines a first parameter related to the plasma chamber, and then determines, based on the first parameter, a first capacitance value for the first electronically variable capacitor and a second capacitance value for the second electronically variable capacitor. The control circuit then generates a control signal to alter the first variable capacitance and the second variable capacitance accordingly, causing the RF power reflected back to the RF source to decrease while the frequency of the RF source is not altered.

In one embodiment, an RF impedance matching circuit is disclosed. The matching circuit is coupled between a plasma chamber and an RF source providing an RF signal having a frequency. The matching circuit includes a first electronically variable capacitor having a first variable capacitance and a second electronically variable capacitor having a second variable capacitance. A control circuit determines a first parameter related to the plasma chamber, and then determines, based on the first parameter, a first capacitance value for the first electronically variable capacitor and a second capacitance value for the second electronically variable capacitor. The control circuit then generates a control signal to alter the first variable capacitance and the second variable capacitance accordingly, causing the RF power reflected back to the RF source to decrease while the frequency of the RF source is not altered.

Systems, devices, and methods for adjusting tuning settings of tunable components, such as tunable capacitors, can be configured for calibrating a tunable component. Specifically, the systems, devices and methods can measure a device response for one or more inputs to a tunable component, store a calibration code in a non-volatile memory that characterizes the device response of the tunable component, and adjust a tuning setting of the tunable component based on the calibration code to achieve a desired response of the tunable component.

Systems, devices, and methods for adjusting tuning settings of tunable components, such as tunable capacitors, can be configured for calibrating a tunable component. Specifically, the systems, devices and methods can measure a device response for one or more inputs to a tunable component, store a calibration code in a non-volatile memory that characterizes the device response of the tunable component, and adjust a tuning setting of the tunable component based on the calibration code to achieve a desired response of the tunable component.

A method of manufacturing a multilayer ceramic electronic component includes preparing a green mother laminate in which ceramic layers and inner electrode layers are stacked; cutting the mother laminate perpendicularly or substantially perpendicularly to a main surface of the mother laminate and in a first direction when the mother laminate is viewed in plan such that first sectional surfaces are formed, and pressing the mother laminate to obtain a bonded laminate in which the first sectional surfaces are bonded to each other; and separating the bonded laminate between the first sectional surfaces to obtain laminates. Then, the bonded laminate is cut perpendicularly or substantially perpendicularly to the main surface and in a second direction that intersects the first sectional surfaces such that second sectional surfaces are formed.

Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

An adjustable sensing capacitance microelectromechanical system (MEMS) apparatus includes an ASIC and a sensing component. The ASIC includes a top surface, a readout circuit and a plurality of electrical switches. The sensing component, configured to sensing physical quantity, includes a fixed electrode and a movable electrode. The fixed electrode includes a plurality of electrode units. The movable electrode is able to be moved relative to the fixed electrode. The electrical switches are respectively and electrically coupled to the electrode units so as to control a working status of each of the electrode units, thereby changing a sensing capacitance of the MEMS sensor.

An adjustable sensing capacitance microelectromechanical system (MEMS) apparatus includes an ASIC and a sensing component. The ASIC includes a top surface, a readout circuit and a plurality of electrical switches. The sensing component, configured to sensing physical quantity, includes a fixed electrode and a movable electrode. The fixed electrode includes a plurality of electrode units. The movable electrode is able to be moved relative to the fixed electrode. The electrical switches are respectively and electrically coupled to the electrode units so as to control a working status of each of the electrode units, thereby changing a sensing capacitance of the MEMS sensor.

Methods and techniques for fabricating layered structures, such as capacitive micromachined ultrasound transducers, as well as the structures themselves. The layered structure has a membrane that includes a polymer-based layer and a top electrode on the polymer-based layer. The membrane is suspended over a closed cavity and may be actuated by applying a voltage between the top electrode and a bottom electrode that may be positioned along or be a bottom of the closed cavity. The layered structure may be fabricated using a wafer bonding process.