A multilayer capacitor and a board having the same mounted thereon are provided. The multilayer capacitor includes a capacitor body including dielectric layers and first and second internal electrodes, and first to sixth surfaces, the first internal electrode being exposed through the third surface and the fifth surface and the second internal electrode being exposed through the fourth surface and the sixth surface; first and second side portions disposed on the fifth and sixth surfaces, respectively, of the capacitor body; first and second external electrodes; a first step-compensating portion disposed on a margin portion in a width direction on the second dielectric layer on which the second internal electrode is formed on the first internal electrode; and a second step-compensating portion disposed on another margin portion in the width direction on the first dielectric layer on which the first internal electrode is disposed on the second internal electrode.

A multilayer capacitor and a board having the same mounted thereon are provided. The multilayer capacitor includes a capacitor body including dielectric layers and first and second internal electrodes, and first to sixth surfaces, the first internal electrode being exposed through the third surface and the fifth surface and the second internal electrode being exposed through the fourth surface and the sixth surface; first and second side portions disposed on the fifth and sixth surfaces, respectively, of the capacitor body; first and second external electrodes; a first step-compensating portion disposed on a margin portion in a width direction on the second dielectric layer on which the second internal electrode is formed on the first internal electrode; and a second step-compensating portion disposed on another margin portion in the width direction on the first dielectric layer on which the first internal electrode is disposed on the second internal electrode.

A ceramic electronic device includes: a ceramic main body having a parallelepiped shape in which edges of first internal electrode layers are led out to a first edge face and edges of second internal electrode layer are led out to a second edge face facing the first edge face; and external electrodes respectively formed on the first edge face and the second edge face and extending to at least one side face of the ceramic main body, wherein a distance in a length direction between first conductive layers of the respective external electrodes on the at least one side face is shorter between locations corresponding to corner portions of the ceramic main body, respectively, than between center portions of the first conductive layers of the respective external electrodes in a width direction orthogonal to the length direction on the at least one side face.

A method of manufacturing a capacitor structure includes the following. A first, second, third, fourth, fifth, sixth and seventh portions of a contact layer arrange from periphery to center. A first-conductive layer contacting the first portion forms in an opening. A first-dielectric layer contacting the second portion forms on the first-conductive layer. A second-conductive layer forms on the first-dielectric layer. A second-dielectric layer contacting the third portion forms on the second-conductive layer. A third-conductive layer contacting the fourth portion forms on the second-dielectric layer. A third-dielectric layer contacting the fifth portion forms on the third-conductive layer. A fourth-conductive layer contacting the second-conductive layer forms on the third-dielectric layer. A fourth-dielectric layer contacting the sixth portion forms on the fourth-conductive layer. A fifth-conductive layer contacting the seventh portion forms on the fourth-dielectric layer. A fifth-dielectric layer forms on the fourth-dielectric layer and the fifth-conductive layer.

A method of manufacturing a capacitor structure includes the following. A first, second, third, fourth, fifth, sixth and seventh portions of a contact layer arrange from periphery to center. A first-conductive layer contacting the first portion forms in an opening. A first-dielectric layer contacting the second portion forms on the first-conductive layer. A second-conductive layer forms on the first-dielectric layer. A second-dielectric layer contacting the third portion forms on the second-conductive layer. A third-conductive layer contacting the fourth portion forms on the second-dielectric layer. A third-dielectric layer contacting the fifth portion forms on the third-conductive layer. A fourth-conductive layer contacting the second-conductive layer forms on the third-dielectric layer. A fourth-dielectric layer contacting the sixth portion forms on the fourth-conductive layer. A fifth-conductive layer contacting the seventh portion forms on the fourth-dielectric layer. A fifth-dielectric layer forms on the fourth-dielectric layer and the fifth-conductive layer.

A high-voltage antiferroelectric and a method for manufacturing the same are provided. The antiferroelectric has a composition of Pb.sub.xLa.sub.1-x([Zr.sub.1-YSn.sub.Y].sub.ZTi.sub.1-Z). The antiferroelectric is sintered at a low temperature, and has a high density and a high breakdown voltage.

A high-voltage antiferroelectric and a method for manufacturing the same are provided. The antiferroelectric has a composition of Pb.sub.xLa.sub.1-x([Zr.sub.1-YSn.sub.Y].sub.ZTi.sub.1-Z). The antiferroelectric is sintered at a low temperature, and has a high density and a high breakdown voltage.

A method for manufacturing a busbar (1), in particular a laminated busbar (1), configured for mounting an electronic component, in particular a passive electronic component such as a capacitor, on the busbar (1), comprising: providing a first conductive layer (11) made from aluminum, providing a first connector element (15) for connecting the first conductive layer (11) and the electronic component, wherein the first connector element (15) is at least partially covered with nickel and/or tin, and creating an bond between the first conductive layer (11) and the first connector element (15) by laser welding.

A method for manufacturing a busbar (1), in particular a laminated busbar (1), configured for mounting an electronic component, in particular a passive electronic component such as a capacitor, on the busbar (1), comprising: providing a first conductive layer (11) made from aluminum, providing a first connector element (15) for connecting the first conductive layer (11) and the electronic component, wherein the first connector element (15) is at least partially covered with nickel and/or tin, and creating an bond between the first conductive layer (11) and the first connector element (15) by laser welding.

A multilayer capacitor and a board having the same mounted thereon are provided. The multilayer capacitor includes a capacitor body including dielectric layers and first and second internal electrodes, and first to sixth surfaces, the first internal electrode being exposed through the third surface and the fifth surface and the second internal electrode being exposed through the fourth surface and the sixth surface; first and second side portions disposed on the fifth and sixth surfaces, respectively, of the capacitor body; first and second external electrodes; a first step-compensating portion disposed on a margin portion in a width direction on the second dielectric layer on which the second internal electrode is formed on the first internal electrode; and a second step-compensating portion disposed on another margin portion in the width direction on the first dielectric layer on which the first internal electrode is disposed on the second internal electrode.