An integrated circuit (IC) includes a substrate and a first capacitor on the substrate. The first capacitor has a first width. A first dielectric layer is provided on a side of the first capacitor opposite the substrate. Further, a second capacitor is present on a side of the first dielectric layer opposite the first capacitor. The second capacitor has a second width that is smaller than the first width. The IC also has a second dielectric layer and a first metal layer. The second dielectric layer is on a side of the second capacitor opposite the first dielectric layer. The first metal layer is on a side of the second dielectric layer opposite the second capacitor.

An integrated circuit (IC) includes a substrate and a first capacitor on the substrate. The first capacitor has a first width. A first dielectric layer is provided on a side of the first capacitor opposite the substrate. Further, a second capacitor is present on a side of the first dielectric layer opposite the first capacitor. The second capacitor has a second width that is smaller than the first width. The IC also has a second dielectric layer and a first metal layer. The second dielectric layer is on a side of the second capacitor opposite the first dielectric layer. The first metal layer is on a side of the second dielectric layer opposite the second capacitor.

A variable capacitor is disclosed. The variable capacitor includes a multi-layer ceramic capacitor member, and a capacitance varying mechanism. The multi-layer ceramic capacitor member includes one or two external electrode(s), a ceramic dielectric, and a plurality of electrode layers positioned inside the ceramic dielectric. The capacitance varying mechanism includes an electrical conductor positioned aside and approximate to the ceramic dielectric. The electrical conductor is deformable responsive to a pressure applied thereon, and an area of the electrical conductor in contact with the ceramic dielectric varies in accordance with the pressure, thus varying a capacitance value between the external electrode(s) and the electrical conductor. In general, the external electrode(s) of the multi-layer ceramic capacitor member serve(s) as fixed electrode(s) of the variable capacitor.

A variable capacitor is provided. The variable capacitor includes a plurality of capacitor segments. The plurality of capacitor segments are connected in parallel within the variable capacitor. When a plurality of candidate capacitances allowable to the variable capacitor according to a connection state of the plurality of capacitor segments connected in parallel are sorted in a magnitude sequence, the plurality of candidate capacitances form a geometric series. The variable capacitor is used for a Voltage Controlled Oscillator (VCO), and the VCO is used for a Phase Locked Loop (PLL).

A variable capacitor is provided. The variable capacitor includes a plurality of capacitor segments. The plurality of capacitor segments are connected in parallel within the variable capacitor. When a plurality of candidate capacitances allowable to the variable capacitor according to a connection state of the plurality of capacitor segments connected in parallel are sorted in a magnitude sequence, the plurality of candidate capacitances form a geometric series. The variable capacitor is used for a Voltage Controlled Oscillator (VCO), and the VCO is used for a Phase Locked Loop (PLL).

A design method applied to a capacitor array is provided. The capacitor array includes multiple preset capacitor units, and each preset capacitor includes multiple unit capacitors. The method includes: acquiring unit simulation models of the preset capacitor units; acquiring a first simulation model of the capacitor array based on an arrangement manner of the preset capacitor units in the capacitor array and the unit simulation models of the preset capacitor unit; acquiring an arrangement direction of the preset capacitor units based on the arrangement manner, establishing a parasitic resistance equivalent test structure of a group of preset capacitor units in the same arrangement direction; obtaining a parasitic resistance of each preset capacitor unit based on the parasitic resistance equivalent test structure; and establishing a second simulation model representing the capacitor array based on the parasitic resistance of each preset capacitor unit and the first simulation model.

An electrical device comprises a substrate, a first dielectric layer, a first die, an adjustable inductor and a second die. The substrate has a first surface. The first dielectric layer is disposed on the first surface of the substrate and has a first surface. The first die is surrounded by the first dielectric layer. The adjustable inductor is electrically connected to the first die. The adjustable inductor comprises a plurality of pillars surrounded by the first dielectric layer, a plurality of first metal strips disposed on the first surface of the first dielectric layer and electrically connected to the pillars, and a plurality of second metal strips disposed on the first surface of the first dielectric layer and electrically connected to the pillars. A width of at least one of the second metal strips is different than a width of at least one of the first metal strips. The second die is electrically connected to the adjustable inductor.

A multilayer electronic component includes a ceramic body having stacked dielectric layers to form a first capacitor part and a second capacitor part, wherein the first capacitor has a constant capacitance, and the second capacitor part has a variable capacitance; a voltage control terminal formed on a lateral surface of the ceramic body; an input terminal disposed on another lateral surface of the ceramic body corresponding to the first capacitor part; and an output terminal disposed on the other lateral surface of the ceramic body corresponding to the second capacitor part separate from the input terminal.

A multilayer electronic component includes a ceramic body having stacked dielectric layers to form a first capacitor part and a second capacitor part, wherein the first capacitor has a constant capacitance, and the second capacitor part has a variable capacitance; a voltage control terminal formed on a lateral surface of the ceramic body; an input terminal disposed on another lateral surface of the ceramic body corresponding to the first capacitor part; and an output terminal disposed on the other lateral surface of the ceramic body corresponding to the second capacitor part separate from the input terminal.

A capacitor system is disclosed that includes a first capacitor with a connection for a first pole and a connection for a second pole and a second capacitor with a connection for a first pole and a connection for a second pole. The first poles are like poles in relation to one another and the second poles are like poles in relation to one another and the first poles are of a polarity different from the second poles. Two different-polarity connections of two capacitors are connected to the capacitors on one side of the capacitor system and lead out from the capacitor system at a substantially constant distance from one another, in parallel and/or in a twisted state.