In an embodiment, a system includes: a base with a bore hole, wherein the base is configured to secure a wafer at a first position on the base; a pin extending through the bore hole; a focus ring horizontally surrounding the wafer at the first position and extending upwardly from the base, wherein the wafer is configured to be moved vertically between the first position and a second position above the focus ring via the pin; and a slit valve above the focus ring, wherein the wafer is configured to be moved horizontally between the second position and the slit valve via a robotic arm.

A method and apparatus for biasing regions of a substrate in a plasma assisted processing chamber are provided. Biasing of the substrate, or regions thereof, increases the potential difference between the substrate and a plasma formed in the processing chamber thereby accelerating ions from the plasma towards the active surfaces of the substrate regions. A plurality of bias electrodes herein are spatially arranged across the substrate support in a pattern that is advantageous for managing uniformity of processing results across the substrate.

A method and apparatus for biasing regions of a substrate in a plasma assisted processing chamber are provided. Biasing of the substrate, or regions thereof, increases the potential difference between the substrate and a plasma formed in the processing chamber thereby accelerating ions from the plasma towards the active surfaces of the substrate regions. A plurality of bias electrodes herein are spatially arranged across the substrate support in a pattern that is advantageous for managing uniformity of processing results across the substrate.

A manufacturing process of an element chip comprises steps of preparing a substrate including a plurality of etching regions and element regions each containing a plurality of convex and concave portions, holding the substrate and a frame with a holding sheet, forming a protective film by applying a first mixture to form a coated film above the substrate and by drying the coated film to form the protective film along the convex and concave portions, the first mixture containing a water-soluble first resin, water and a water-soluble organic solvent and has a vapor pressure higher than water, removing the protective film by irradiating a laser beam thereon to expose the substrate in the etching regions, plasma-etching the substrate along the etching regions while maintaining the protective film in the element regions to individualize the substrate, and removing the protective film by contacting the protective film with an aqueous rinse solution.

A manufacturing process of an element chip comprises steps of preparing a substrate including a plurality of etching regions and element regions each containing a plurality of convex and concave portions, holding the substrate and a frame with a holding sheet, forming a protective film by applying a first mixture to form a coated film above the substrate and by drying the coated film to form the protective film along the convex and concave portions, the first mixture containing a water-soluble first resin, water and a water-soluble organic solvent and has a vapor pressure higher than water, removing the protective film by irradiating a laser beam thereon to expose the substrate in the etching regions, plasma-etching the substrate along the etching regions while maintaining the protective film in the element regions to individualize the substrate, and removing the protective film by contacting the protective film with an aqueous rinse solution.

A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.

A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.

A copper plasma etching method according an exemplary embodiment includes: placing a substrate on a susceptor in a process chamber of a plasma etching apparatus; supplying an etching gas that include hydrogen chloride into the process chamber; plasma-etching a conductor layer that include copper in the substrate; and maintaining a temperature of the susceptor at 10 C. or less during the plasma-etching.

A copper plasma etching method according an exemplary embodiment includes: placing a substrate on a susceptor in a process chamber of a plasma etching apparatus; supplying an etching gas that include hydrogen chloride into the process chamber; plasma-etching a conductor layer that include copper in the substrate; and maintaining a temperature of the susceptor at 10 C. or less during the plasma-etching.

A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.