A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.

A method for preparing a sample for transmission electron microscopy (TEM) comprises providing a substrate having a patterned area on its surface that is defined by a particular topography. A conformal layer of contrasting material is deposited on the topography by depositing a layer of the contrasting material on a local target area of the substrate, spaced apart from the patterned area via Electron Beam Induced Deposition (EBID). The deposition parameters, the thickness of the layer deposited in the target area, and the distance of the target area to the patterned area are selected so that a conformal layer of the contrasting material is formed on the topography of the patterned area. A protective layer is subsequently deposited. The protective layer does not damage the topography in the patterned area because the patterned area is protected by the conformal layer.

A beam irradiation device that irradiates a plurality of electron beams includes a multibeam optical system that emits the plurality of beams to be irradiated on a target; and a controller that controls an irradiation state of each of the plurality of beams in accordance with change in a relative position between the target and the multibeam optical system, and based on the irradiation state of a first beam of the plurality of beams, controls the irradiation state of a second beam of the plurality of beams.

In one embodiment, a charged particle beam writing method is for writing a pattern in a writing area on a substrate by irradiating a charged particle beam onto the substrate while moving the substrate to write stripes sequentially, each of the stripes having a width W and shapes obtained by dividing the writing area by the width W. The method includes performing S times (S is an integer greater than or equal to two) strokes, each of the strokes which is a process writing the stripes in a multiplicity of 2n (n is an integer greater than or equal to one) while shifting a reference point of each of the stripes in the width direction by a preset stripe shift amount and changing a moving direction of the substrate for each of the stripes, and writing while the reference point of the stripes in the each of the strokes in the width direction of the stripes is shifted by a preset stroke shift amount in each of the strokes.

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Apparatus and methods to control the phase of power sources for plasma process regions in a batch process chamber. A master exciter controls the phase of the power sources during the process sequence based on feedback from the match circuits of the respective plasma sources.

A method and apparatus for biasing regions of a substrate in a plasma-assisted processing chamber are provided. Biasing of the substrate, or regions thereof, increases the potential difference between the substrate and a plasma formed in the processing chamber thereby accelerating ions from the plasma towards the active surfaces of the substrate regions. A plurality of bias electrodes herein are spatially arranged across the substrate support in a pattern that is advantageous for managing uniformity of processing results across the substrate.

A method and apparatus for biasing regions of a substrate in a plasma-assisted processing chamber are provided. Biasing of the substrate, or regions thereof, increases the potential difference between the substrate and a plasma formed in the processing chamber thereby accelerating ions from the plasma towards the active surfaces of the substrate regions. A plurality of bias electrodes herein are spatially arranged across the substrate support in a pattern that is advantageous for managing uniformity of processing results across the substrate.

Disclosed is an object table for holding an object, comprising: an electrostatic clamp arranged to clamp the object on the object table; a neutralizer arranged to neutralize a residual charge of the electrostatic clamp; a control unit arranged to control the neutralizer, wherein the residual charge is an electrostatic charge present on the electrostatic clamp when no voltage is applied to the electrostatic clamp.