H01L21/00

Die stacking structure and method forming same

A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors.

Space efficient flip chip joint design
11521947 · 2022-12-06 · ·

An apparatus includes an Integrated Circuit (IC). A first pillar includes a first end and a second end. The first end is connected to the IC and the second end includes a first attachment point collinear with a first central axis of the first pillar. The first attachment point includes a first solder volume capacity. A second pillar includes a third end and a fourth end. The third end is connected to the IC and the fourth end includes a second attachment point disposed on a side of the second pillar facing the first pillar. The second attachment point includes a second solder volume capacity being less than the first solder volume capacity. A first distance between the first end and the second end is less than a second distance between the third end and the fourth end.

Semiconductor device with bit line contact and method for fabricating the same

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first bit line structure positioned above the substrate and including a first line portion arranged in parallel to a first direction, and a second line portion connecting to a first end of the first line portion and arranged in parallel to a second direction in perpendicular to the first direction; a first bit line top contact including a first bar portion positioned on the first end of the first line portion and arranged in parallel to the first direction, and a second bar portion connecting to a first end of the first bar portion, positioned on the second line portion, and arranged in parallel to the second direction; and a first top conductive layer electrically coupled to the first bit line top contact.

Method of determining control parameters of a device manufacturing process

A method for determining a metric of a feature on a substrate obtained by a semiconductor manufacturing process involving a lithographic process, the method including: obtaining an image of at least part of the substrate, wherein the image includes at least the feature; determining a contour of the feature from the image; determining a plurality of segments of the contour; determining respective weights for each of the plurality of segments; determining, for each of the segments, an image-related metric; and determining the metric of the feature in dependence on the weights and the calculated image-related metric of each of the segments.

Method of determining control parameters of a device manufacturing process

A method for determining a metric of a feature on a substrate obtained by a semiconductor manufacturing process involving a lithographic process, the method including: obtaining an image of at least part of the substrate, wherein the image includes at least the feature; determining a contour of the feature from the image; determining a plurality of segments of the contour; determining respective weights for each of the plurality of segments; determining, for each of the segments, an image-related metric; and determining the metric of the feature in dependence on the weights and the calculated image-related metric of each of the segments.

Plurality of heat sinks for a semiconductor package

Various embodiments may provide a semiconductor package. The semiconductor package may include a first electrical component, a second electrical component, a first heat sink, and a second heat sink bonded to a first package interconnection component and a second package interconnection component. The first package interconnection component and the second package interconnection component may provide lateral and vertical interconnections in the package.

Capacitively coupled plasma etching apparatus

Disclosed is a capacitively coupled plasma etching apparatus, wherein an electrically conductive supporting rod where a lower electrode is fixed is connected to driving means, the driving means driving the electrically conductive support rod to move axially; besides, the lower electrode is fixed to the bottom of a chamber body via a retractable sealing part, causing the upper surface of the lower electrode to be hermetically sealed in an accommodation space in the chamber body; an electrical connection part is connected on the chamber body; the radio frequency current in the chamber body returns, via the electrical connection part, to the loop end of a radio frequency matcher. In this way, the lower electrode is fixed on the chamber body via the retractable sealing part, such that when the lower electrode is driven by the driving means to move up/down, the chamber body does not move along with it, and the radio frequency loop in the chamber body is in a steady state, thereby achieving stability of the radio frequency loop while implementing adjustability of the plate distance.

Cleaning method in inspection apparatus, and the inspection apparatus
11515141 · 2022-11-29 · ·

A cleaning method in an inspection apparatus that performs an electrical characteristic inspection on a device under test formed in an inspection object, includes: transferring, in a transfer process, a stage on which the inspection object is mounted to a position facing a probe card having probes, the probes being brought into contact with the device under test during the electrical characteristic inspection; subsequently, exhausting and depressurizing a space between the probe card and the stage facing the probe card in a peeling-off preparation process; introducing a gas into the space which has been depressurized and peeling off foreign substances adhering to a front surface of the stage and the probes in a foreign substance peeling-off process; and exhausting the space to discharge the foreign substances while continuously introducing the gas into the space in a foreign substance discharging process.

Low defect nuclear transmutation doping in nitride-based semiconductor materials

Doped nitride-based semiconductor materials and methods of producing these materials are described herein.

Method of etching object
11515172 · 2022-11-29 · ·

In a first aspect of a present inventive subject matter, a method of etching an object to be etched with an etching liquid that contains bromine, and the object contains at least gallium and/or aluminum.