A method for efficiently waking up ferroelectric memory is provided. A wafer is formed with a plurality of first signal lines, a plurality of second signal lines, a plurality of third signal lines, and a plurality of ferroelectric memory cells that constitute a ferroelectric memory array. Each of the ferroelectric memory cells is electrically connected to one of the first signal lines, one of the second signal lines and one of the third signal lines. Voltage signals are simultaneously applied to the first signal lines, the second signal lines and the third signal lines to induce occurrence of a wake-up effect in the ferroelectric memory cells.

A transparent display device may have high transmittance and at the same time embody high resolution. Moreover, the transparent display device may provide optimal picture quality. The transparent display device comprises a plurality of first signal lines extended in a first direction and disposed to be spaced apart from one another, a plurality of second signal lines extended in a second direction and disposed to be spaced apart from one another, a transmissive area provided between two first signal lines adjacent to each other and two second signal lines adjacent to each other, and a pixel disposed in an intersection or overlapping area where the first signal line and the second signal line cross or overlap each other, including a first subpixel emitting light of a first color, a second subpixel emitting light of a second color, and a third subpixel emitting light of a third color. The pixel includes a first pixel overlapped with a part of the first signal line of an odd row and a second pixel overlapped with a part of the first signal line of an even row, and the first pixel and the second pixel are different from each other in a position of at least one of the first subpixel, the second subpixel or the third subpixel.

A semiconductor device includes a first integrated circuit and a second integrated circuit disposed on a semiconductor substrate and spaced apart from each other. A wiring structure is disposed on the semiconductor substrate and electrically connects the first integrated circuit and the second integrated circuit. A first TSV area and a second TSV area are disposed between the first integrated circuit and the second integrated circuit The first and second TSV areas include a plurality of first and second TSV structures penetrating through the semiconductor substrate, respectively. The wiring structure passes between the first TSV area and the second TSV area.

Embodiments of the present disclosure provide a method of manufacturing a magnetic random access memory (MRAM) and a MRAM. The method includes: preparing a bottom electrode through hole, a bottom electrode, a magnetic tunnel junction (MTJ), a top electrode, and an insulating layer sequentially on a semiconductor substrate; forming a first interlayer dielectric layer on the insulating layer; forming an etching stop layer on the first interlayer dielectric layer; forming a second interlayer dielectric layer on the etching stop layer; etching a part of the second interlayer dielectric layer above the top electrode to the etching stop layer, and forming a first trench; performing a self-alignment implantation inclined on a part of the first interlayer dielectric layer corresponding to a bottom of the first trench; continuously etching through the first trench to a top end surface of the top electrode, and forming a second trench.

A method, apparatus and system with an autonomic, self-healing polymer capable of slowing crack propagation within the polymer and slowing delamination at a material interface.

There is provided a semiconductor device comprising: a semiconductor substrate including a drift region of a first conductivity type; an emitter region of the first conductivity type provided above the drift region inside the semiconductor substrate and having a doping concentration higher than the drift region; a base region of a second conductivity type provided between the emitter region and the drift region inside the semiconductor substrate; a first accumulation region of the first conductivity type provided between the base region and the drift region inside the semiconductor substrate and having a doping concentration higher than the drift region; a plurality of trench portions provided to pass through the emitter region, the base region and first accumulation region from an upper surface of the semiconductor substrate, and provided with a conductive portion inside; and a capacitance addition portion provided below the first accumulation region to add a gate-collector capacitance thereto.

A detection method includes: determining process data of a new process; according to the process data of the new process, detecting, by a first production system, whether a wafer carrier type of the new process matches an acceptable level of a corresponding process step or not and whether the new process matches a flag of the corresponding process step or not; if not, determining that the process data does not pass the detection and outputting first detection information; or if the wafer carrier type of the new process matches the acceptable level of the corresponding process step and the new process matches the flag of the corresponding process step, detecting, by a second production system, if the second production system detects a mismatch, determining that the process data does not pass the detection and outputting second detection information.

A piezoelectric element includes a piezoelectric element body including a first principal surface and a second principal surface opposing each other, and a plurality of external electrodes disposed on the first principal surface. A vibration member includes a third principal surface opposing the second principal surface. The piezoelectric element is joined to the third principal surface. A wiring member is electrically connected to the piezoelectric element. The wiring member includes a region located on the plurality of external electrodes and joined to the plurality of external electrodes. The region of the wiring member monolithically covers the plurality of external electrodes when viewed from a direction orthogonal to the first principal surface.

Embodiments are described herein to reshape spacer profiles to improve spacer uniformity and thereby improve etch uniformity during pattern transfer associated with self-aligned multiple-patterning (SAMP) processes. For disclosed embodiments, cores are formed on a material layer for a substrate of a microelectronic workpiece. A spacer material layer is then formed over the cores. Symmetric spacers are then formed adjacent the cores by reshaping the spacer material layer using one or more directional deposition processes to deposit additional spacer material and using one or more etch process steps. For one example embodiment, one or more oblique physical vapor deposition (PVD) processes are used to deposit the additional spacer material for the spacer profile reshaping. This reshaping of the spacer profiles allows for symmetric spacers to be formed thereby improving etch uniformity during subsequent pattern transfer processes.

According to one embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer, and first and second external electrodes. The conductive substrate has a first main surface provided with recess(s), a second main surface, and an end face extending between edges of the first and second main surfaces. The conductive layer covers the first main surface and side walls and bottom surfaces of the recess(s). The dielectric layer is interposed between the conductive substrate and the conductive layer. The first external electrode includes a first electrode portion facing the end face and is electrically connected to the conductive layer. The second external electrode includes a second electrode portion facing the end face and is electrically connected to the conductive substrate.