A transistor device includes a semiconductor structure, source and drain contacts on the semiconductor structure, a gate on the semiconductor structure between the source and drain contacts, and a surface passivation layer on the semiconductor structure between the gate and the source or drain contact. The surface passivation layer includes an opening therein that exposes a first region of the semiconductor structure for processing the first region differently than a second region of the semiconductor structure adjacent the gate. Related devices and fabrication methods are also discussed.

A method of forming a high electron mobility transistor (HEMT) includes: providing a semiconductor structure comprising a channel layer and a barrier layer sequentially stacked on a substrate; forming a first insulating layer on the barrier layer; and forming a gate contact, a source contact, and a drain contact on the barrier layer. An interface between the first insulating layer and the barrier layer comprises a modified interface region on a drain access region and/or a source access region of the semiconductor structure such that a sheet resistance of the drain access region and/or the source access region is between 300 and 400 Ω/sq.

A package structure including a bottom die, a first die, a second die, an encapsulant and a first dummy structure is provided. The first die and a second die are bonded to a first side of the bottom die. The encapsulant laterally encapsulates the first die and the second die. The first dummy structure is bonded to the first side of the bottom die, wherein a sidewall of the first dummy structure is coplanar with a first sidewall of the bottom die.

n electro-optic assembly includes a layer of electro-optic material configured to switch optical states upon application of an electric field and an anisotropically conductive layer having one or more moisture-resistive polymers and a conductive material, the moisture-resistive polymer having a WVTR less than 5 g/(m.sup.2*d).

Provided is a method for manufacturing a semiconductor device suitable for achieving low wiring resistance between semiconductor elements that is bonded via an adhesive layer and multi-layered. The method according to the present invention is as follows. First, a wafer laminate (W) is prepared, the wafer laminate (W) including a wafer (10) having a circuit forming surface (10a), a wafer (20) having a main surface (20a) and a back surface (20b), and an adhesive layer (30) containing an SiOC-based polymer. Then, a hole (H) is formed in the wafer laminate (W) by etching the wafer laminate (W) from the wafer (20) side via a mask pattern masking a portion of the main surface (20a) side of the wafer (20), the hole (H) extending through the wafer (20) and the adhesive layer (30) and reaching a wiring pattern (12b) in the wafer (10). Then, an insulating film (41) is formed on an inner surface of the hole (H). Then, the insulating film (41) on a bottom surface of the hole (H) is removed. Then, the wafer laminate (W) is subjected to a cleaning treatment (an oxygen plasma treatment and/or an Ar sputtering treatment). Then, a conductive portion is formed in the hole (H).

An electronic device comprises a target substrate, a micro semiconductor structure array, a conductor array, and a connection layer. The micro semiconductor structure array is disposed on the target substrate. The conductor array corresponds to the micro semiconductor structure array, and electrically connects the micro semiconductor structure array to a pattern circuit of the target substrate. The conductors of the conductor array are independent from one another. Each conductor is an integrated member formed by eutectic bonding a conductive pad of the target substrate and a conductive electrode of the corresponding one of the micro semiconductor structures of the micro semiconductor structure array. The connection layer connects the micro semiconductor structures to the target substrate. The connection layer excludes a conductive material. The connection layer contacts and surrounds the conductors, so that the connection layer and the conductors together form a one-layer structure.

A substrate includes a metal component on a surface. A polymeric layer is deposited on the surface using molecular layer deposition. The polymeric layer includes a metalcone and has a thickness from 1 nm to 20 nm. The polymeric layer is stable at room temperature, but will undergo a structural change at high temperatures. The polymeric layer can be annealed to cause a structural change, which can occur during soldering.

An electronic component transferring apparatus is configured to transfer an electronic component on a flexible carrier onto a target substrate. The electronic component transferring apparatus includes a first frame configured to carry the flexible carrier, a second frame configured to carry the target substrate, an abutting component arranged adjacent to the flexible carrier, an actuating mechanism, an energy generating device, and an optical sensing module. The actuating mechanism is configured to actuate the abutting component and move the abutting component in a direction of the flexible carrier, such that an abutting end of the abutting component abuts against the flexible carrier. The energy generating device is configured to generate an energy beam penetrating at least a portion of the abutting component and being directed towards the flexible carrier from the abutting end of the abutting component. The optical sensing module is configured to perform sensing through the abutting component.

A stacked semiconductor device encompasses a mother-substrate, rectangular chips mounted on the mother-substrate, and bump-connecting mechanisms connecting the mother-substrate and the chips by a non-provisional joint-process with a height lower than the height of a provisional joint-process jointing the mother-substrate and the chips. The mother-substrate has unit elements arranged in each of unit-element areas assigned to a first lattice defined on a first main surface of the mother-substrate, the first main surface is divided into chip-mounting areas along a second lattice having a smaller number of meshes than the first lattice. The bump-connecting mechanisms are arranged along a third lattice corresponding to the arrangement of the unit elements, and transmit signals from the unit elements independently to each of the circuits merged in the chips. After the provisional joint-process, the bump-connecting mechanisms can be separated into substrate-side and chip-side connection-elements.

The present invention relates to a field of photonic integrated circuits, which provides a semiconductor device. In some embodiments, the semiconductor device includes: a PIC chip including a conductive structure in a via; a first electronic integrated circuit chip (i.e., first EIC chip) arranged on a first surface of the PIC chip; a second electronic integrated circuit chip (i.e., second EIC chip) arrange on a second surface of the PIC chip; wherein the first EIC chip is electrically connected to the second EIC chip through the conductive structure in the via of the PIC chip. The semiconductor device of the present invention optimizes wiring of the PIC chip and can suppress a voltage drop caused by quite a long wire, optimizing a package structure.