Methodologies and a device for SRAM patterning are provided. Embodiments include forming a spacer layer over a fin channel, the fin channel being formed in four different device regions; forming a bottom mandrel over the spacer layer; forming a top mandrel directly over the bottom mandrel, wherein the top and bottom mandrels including different materials; forming a buffer oxide layer over the top mandrel; forming an anti-reflective coating (ARC) over the first OPL; forming a photoresist (PR) over the ARC and patterning the PR; and etching the first OPL, ARC, buffer oxide, and top mandrel with the pattern of the PR, wherein a pitch of the PR as patterned is different in each of the four device regions.

A semiconductor device includes a semiconductor substrate including a first source/drain region formed in an upper portion of the semiconductor substrate, a metal silicide layer that covers a top surface of the first source/drain region, and a semiconductor pillar that penetrates the metal silicide layer and is connected to the semiconductor substrate. The semiconductor pillar includes a second source/drain region formed in an upper portion of the semiconductor pillar, a gate electrode on the metal silicide layer, with the gate electrode surrounding the semiconductor pillar in a plan view. A contact is connected to the metal silicide layer.

A method of forming fine patterns includes forming pillars arrayed in rows and columns on an underlying layer and forming a spacer layer on the underlying layer to cover the pillars. Portions of the spacer layer respectively covering the pillars arrayed in each row or in each column are in contact with each other to provide first interstitial s paces disposed between the pillars arrayed in a diagonal direction between a row direction and a column direction as well as to provide cleavages at corners of each of the first interstitial spaces in a plan view. A healing layer is formed on the spacer layer to fill the cleavages of the first interstitial spaces. The healing layer is formed to provide second interstitial spaces respectively located in the first interstitial spaces as well as to include a polymer material.

Described is an apparatus which comprises: a pad; a first transistor coupled in series with a second transistor and coupled to the pad; and a self-biasing circuit to bias the first transistor such that the first transistor is to be weakly biased during an electrostatic discharge (ESD) event. Described is also an apparatus which comprises: a first transistor; and a first local ballast resistor formed of a trench contact (TCN) layer, the first local ballast resistor having a first terminal coupled to either the drain or source terminal of the first transistor.

A semiconductor memory device includes a stacked body including a first electrode layer and a second electrode layer stacked on the first electrode layer, and first and second interconnections on a first surface of the stacked body. The first and second electrode layers have first and second end surfaces respectively in the first surface. The first interconnection is electrically connected to the first electrode layer through a first region of the first end surface; and the second interconnection is electrically connected to the second electrode layer through a second region of the second end surface. The first and second interconnections extend in a first direction on the first surface. The first and second regions are arranged in a second direction crossing the first direction with a crossing angle smaller than 90 degrees. The first region and the second region each have a boundary along the second direction.

According to an embodiment, a semiconductor memory device comprises: control gate electrodes stacked above a substrate; a semiconductor layer that extends in a first direction above the substrate and faces the control gate electrodes; and a gate insulating layer provided between these control gate electrode and semiconductor layer. The gate insulating layer comprises: a first insulating layer covering a side surface of the semiconductor layer; a charge accumulation layer covering a side surface of this first insulating layer; and a second insulating layer including a metal oxide and covering a side surface of this charge accumulation layer. The charge accumulation layer has: a first portion facing the control gate electrode; and a second portion facing a region between control gate electrodes adjacent in the first direction and including more oxygen than the first portion.

This nonvolatile semiconductor memory device includes: a memory cell array including a memory cell; a wiring part connecting the memory cell array to an external circuit; and a transistor that connects the wiring part and the external circuit, the transistor including: a first insulating layer including a first region, a second region, and a third region, the second and third regions being disposed on both sides of the first region, and a height of an upper surface of the first region being lower than those of the second region and the third region; a semiconductor layer disposed along upper surfaces of the first region, the second region, and the third region; and a gate electrode layer disposed via the semiconductor layer and a gate insulating film, on an upper part of the second region.

A semiconductor memory device according to an embodiment includes: a first semiconductor layer, a stacked body including a plurality of conductive layers and a plurality of interlayer insulating layers stacked in a first direction above the first semiconductor layer, a second semiconductor layer opposing the plurality of conductive layers, the second semiconductor layer has a longitudinal direction in the first direction, and a memory insulating layer including a charge accumulation layer and positioned between the second semiconductor layer and the plurality of conductive layers. A thickness in the first direction of at least a first conductive layer as one of the plurality of conductive layers is larger than a thickness in the first direction of another one of the plurality of conductive layers, and the first conductive layer is adjacent to the first semiconductor layer via one of the interlayer insulating layers.

According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, and a columnar portion. The stacked body includes a first insulating layer provided on the substrate, a first electrode layer provided on the first insulating layer and including polycrystalline silicon, a second insulating layer provided on the first electrode layer, and a second electrode layer provided on the second insulating layer. The columnar portion includes a semiconductor layer extending in a stacking direction of the stacked body and a memory layer provided between the semiconductor layer and the stacked body. The first and second electrode layers respectively have a first thickness and a second thickness in the stacking direction, and the first thickness of the first electrode layer is thicker than the second thickness of the second electrode layer.

According to an embodiment, a semiconductor memory device comprises: an insulating layer disposed on a semiconductor substrate; a plurality of memory cell arrays being arranged three-dimensionally on the insulating layer and including a plurality of conductive layers stacked in a first direction that intersects a surface of the semiconductor substrate; and a block insulating layer covering a side surface of one of the plurality of conductive layers. A high permittivity layer is provided between the insulating layer and a lowermost layer of the plurality of conductive layers. A permittivity of the high permittivity layer is much higher than that of the insulating layer.