A semiconductor device may include a linear gate trench that crosses an active region of a substrate of the semiconductor device. The active region may include a plurality of gate areas at a bottom of the gate trench and junction areas at a surface of the substrate in a central portion and opposite end portions of the active region. A conductive line may be in a lower portion of the gate trench. The conductive line may include a gate line and a capping layer that at least partially isolates the gate line from an upper surface of the conductive line. A sealing line may be in an upper portion of the gate trench. The sealing line may cover the conductive line and a surface of the sealing line may be coplanar with the junction areas.

Devices and methods of fabricating integrated circuit devices with reduced cell height are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a logic area and an SRAM area, a fin material layer, and a hardmask layer; depositing a mandrel over the logic area; depositing a sacrificial spacer layer; etching the sacrificial spacer layer to define a sacrificial set of vertical spacers; etching the hardmask layer; leaving a set of vertical hardmask spacers; depositing a first spacer layer; etching the first spacer layer to define a first set of vertical spacers over the logic area; depositing an SOH layer; etching an opening in the SOH layer over the SRAM area; depositing a second spacer layer; and etching the second spacer layer to define a second set of spacers over the SRAM area.

A charge array wafer includes a plurality of electrical charge storage cells disposed in an array configuration. A programmable amount of charge in each of the electrical charge storage cells causes a predetermined electric field to extend from a charge storage layer, through a passivation layer and into the space above the passivation layer, and the predetermined electric field is operable to attract deposition material to the top surface of the passivation layer. The deposition material may be a gas, a liquid or a powder, having a minimum feature size ranging from tens of nanometers to around five microns. The array of electrical charge storage cells includes an uninterrupted two-dimensional array extending over greater than 100×100 electrical charge storage cells without a select gate and without a bit-line contact positioned between any of the electrical charge storage cells.

A synchronous switching converter has an integrated semiconductor device. The integrated semiconductor device has a first semiconductor component and a second semiconductor component coupled in parallel. The first semiconductor component has MOSFET cells with body diodes, and the second semiconductor component has diode cells or MOSFET cells with a low forward voltage. Cells of the second semiconductor component distribute among the first semiconductor component unevenly according to a distribution of a current flowing through the integrated semiconductor device.

A graphene wiring structure of an embodiment has a multilayered graphene having a plurality of planar graphene sheets laminated, and a first interlayer substance being a metal oxyhalide between the plurality of planar graphene sheets.

A semiconductor structure is disclosed that includes a semiconductor structure includes an active area, a first conductive line, a conductive via, a first conductive metal segment coupled to the conductive line through the conductive via, a second conductive metal segment disposed over the active area, and a local conductive segment configured to couple the first conductive metal segment and the second conductive metal segment.

Disclosed are a package structure of an integrated passive device and a manufacturing method thereof and a substrate. The method includes: providing an organic frame having a chip embedding cavity and a metal pillar, laminating at least one layer of first dielectric on an upper surface of the organic frame, and processing the first dielectric by photolithography to form an opening correspondingly above the chip embedding cavity; mounting an electronic component in the chip embedding cavity through the opening, the electronic component including an upper and lower electrodes; laminating and curing a second dielectric into the chip embedding cavity and on an upper surface of the first dielectric, thinning the first and second dielectrics to expose the upper and lower electrodes, upper and lower surfaces of the metal pillar; performing metal electroplating to form a circuit layer communicated with the upper and lower electrodes and the metal pillar.

A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.

A method of performing an operation on a non-volatile memory (NVM) cell of a memory device is disclosed. The pass transistor of the NVM cell is an asymmetric transistor including a source with a halo implant. The source of the pass transistor is coupled to a common source line (CSL) that is shared among NVM cells of a sector of NVM cells. The operation may be performed by applying a first signal to a word line (WLS) coupled to a gate of a memory transistor of the NVM cell and applying a second signal to a bit line (BL) coupled to a drain of the memory transistor of the NVM cell.