Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

A miniaturized transistor with reduced parasitic capacitance and highly stable electrical characteristics is provided. High performance and high reliability of a semiconductor device including the transistor is achieved. A first conductor is formed over a substrate, a first insulator is formed over the first conductor, a layer that retains fixed charges is formed over the first insulator, a second insulator is formed over the layer that retains fixed charges, and a transistor is formed over the second insulator. Threshold voltage V.sub.th is controlled by appropriate adjustment of the thicknesses of the first insulator, the second insulator, and the layer that retains fixed charges.

A method for forming a V-NAND device is disclosed. Specifically, the method involves deposition of at least one of semiconductive material, conductive material, or dielectric material to form a channel for the V-NAND device. In addition, the method may involve a pretreatment step where ALD, CVD, or other cyclical deposition processes may be used to improve adhesion of the material in the channel.

A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.

A method that includes operations below and at least one of the operations is performed by a processor. Whether at least one condition is present in a signal to be received or transmitted by a terminal of a cell of an integrated circuit is determined. When the at least one condition is present in the signal, a plurality of conductive segments of the integrated circuit is assigned, to transmit the signal to the terminal of the cell. Each conductive segment of a first set of conductive segments of the plurality of conductive segments has a first predetermined width, and a distance between adjacent two conductive segments of the first set of conductive segments is greater than the first predetermined width.

An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.

A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction. The active columns, the charge-trapping material and the conductors together form a plurality of thin film transistors, with each thin film transistor formed by one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions. The thin film transistors associated with each active column are organized into one or more vertical NOR strings.

A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a stacked body having a plurality of first insulating layers and conductive layers stacked alternately on the semiconductor substrate; a columnar semiconductor layer contacting the semiconductor substrate in the stacked body being provided extending in a stacking direction of the stacked body and including a first portion and a second portion which is provided above the first portion; a memory layer provided on a side surface of the columnar semiconductor layer facing the stacked conductive layers and extending along the columnar semiconductor layer; and a second insulating layer provided between one of the first insulating layer and the conductive layers of the stacked body. The columnar semiconductor layer has a boundary of the first portion and the second portion, the boundary being close to the second insulating layer; and an average value of an outer diameter of the memory layer facing a side surface of the second insulating layer is larger than that of of the memory layer facing a side surface of a lowermost layer of the first insulating layers in the second portion.

A method includes: disposing a first conductive segment; disposing a first conductive via above the first conductive segment; disposing a first conductive line above the first conductive via; and disposing a second conductive segment electrically coupled to the first conductive line through a third conductive segment, the first conductive segment, and the first conductive via.

An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.