Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

A non-volatile programmable bitcell has a read enable device with a source coupled with a bitline, an anti-fuse device with a gate coupled with a first write line, a drain coupled with a supply voltage and a source coupled with a drain of the read enable device. The bitcell has a fuse device coupled between a second write line and the drain of the read enable device. A magnitude of current flowing in the bitline, when the read enable device is enabled for reading, is dependent both on (1) a voltage level applied to the first write line and anti-fuse device state and on (2) a voltage level applied to the second write line and fuse device state. Usages include in a memory array, such as for FPGA configuration memory. The bitcell can be used as a multi-time programmable element, or to store multiple bit values.

An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.

A trench capacitor includes a plurality of trenches in a semiconductor substrate. A first polysilicon layer is located within the plurality of trenches and over a top surface of the substrate. The first polysilicon layer is continuous between the plurality of trenches. The trench capacitor further includes a plurality of second polysilicon layers. Each of the second polysilicon layers fills a corresponding trench of the plurality of trenches. The second polysilicon layers each extend to a top surface of the first polysilicon layer.

A system includes at least one Input/Output (I/O) interface and a processor. The processor is coupled to the at least one I/O interface. The processor is configured to perform, according to a file or a rule inputted from the at least one I/O interface, operations below. When the at least one condition is present in a signal to be received or transmitted by a terminal of a cell, a plurality of conductive segments is assigned to the terminal of the cell, to transmit the signal to the terminal of the cell. When the at least one condition one is not present in the signal, a single route is assigned to the terminal of the cell, to transmit the signal to the terminal of the cell. The single route and each of the conductive segments are configured to have the same width.

A method for forming a V-NAND device is disclosed. Specifically, the method involves deposition of at least one of semiconductive material, conductive material, or dielectric material to form a channel for the V-NAND device. In addition, the method may involve a pretreatment step where ALD, CVD, or other cyclical deposition processes may be used to improve adhesion of the material in the channel.

A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.

A method of writing data into a volatile thyristor memory cell array and maintaining the data with refresh is disclosed.

An integrated circuit structure includes an SRAM array including a first sub-array having a first plurality of rows and a plurality of columns of SRAM cells, and a second sub-array having a second plurality of rows and the plurality of columns of SRAM cells. A first bit-line and a first complementary bit-line are connected to the first and the second pass-gate MOS devices of SRAM cells in a column in the first sub-array. A second bit-line and a second complementary bit-line are connected to the first and the second pass-gate MOS devices of SRAM cells in the column in the second sub-array. The first bit-line and the first complementary bit-line are disconnected from the second bit-line and the second complementary bit-line. A sense amplifier circuit is electrically coupled to, and configured to sense, the first bit-line, the first complementary bit-line, the second bit-line, and the second complementary bit-line.

An SRAM device includes first, second and third transistors, which are used as a pass gate transistor, a pull-down transistor, and a pull-up transistor, respectively. A channel region of each transistor may include a plurality of semiconductor sheets that are vertically stacked on a substrate. The semiconductor sheets used as the channel regions of the first and second transistors may have a width greater than the semiconductor sheets used as channel regions of the third transistor.