A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device, a second pass gate device, a third pass gate device and a fourth pass gate device disposed on a substrate. A plurality of fin structures is disposed on the substrate, the fin structures including at least one first fin structure and at least one second fin structure. A step-shaped structure is disposed on the substrate, including a first part, a second part and a bridge part. A first extending contact feature crosses over the at least one first fin structure and the at least one second fin structure.

The non-volatile memory device comprises memory cells each comprising a selectable state transistor having a floating gate and a control gate. The state transistor is of the depletion-mode type and is advantageously configured so as to have a threshold voltage that is preferably negative when the memory cell is in a virgin state. When the memory cell is read, a read voltage of zero may then be applied to the control gate and also to the control gates of the state transistors of all the memory cells of the memory device.

A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.

A non-volatile memory device may include a semiconductor substrate, a ferroelectric layer, a source, a drain, a gate and a channel region. The semiconductor substrate may have a recess. The ferroelectric layer may be formed in the recess. The source may be arranged at a first side of the recess. The drain may be arranged at a second side of the recess opposite to the first side. The gate may be arranged on the ferroelectric layers. The channel region may be formed on the recess between the source and the drain.

The present disclosure provides in one aspect a semiconductor device including an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which, in turn, is formed on a base substrate material, a gate structure formed on the active semiconductor layer, and a back gate region provided in the base substrate material below the gate structure opposing the gate structure. Herein, the back gate region may be electrically insulated from the surrounding base substrate material via an isolation region surrounding the back gate region.

Devices and methods of fabricating integrated circuit devices using semi-bidirectional patterning are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a dielectric layer, a first hardmask layer, a second hardmask layer, a third hardmask layer, and a lithography stack; patterning a first set of lines; patterning a second set of lines between the first set of lines; etching to define a combination of the first and second set of lines; depositing a second lithography stack; patterning a third set of lines in a direction perpendicular to the first and second set of lines; etching to define the third set of lines, leaving an OPL; depositing a spacer over the OPL; etching the spacer, leaving a vertical set of spacers; and etching the second hardmask layer using the third hardmask layer and the set of vertical spacers as masks.

The present disclosure provides, in accordance with some illustrative embodiments, a semiconductor device structure including a hybrid substrate comprising an SOI region and a bulk region, the SOI region comprising an active semiconductor layer, a substrate material, and a buried insulating material interposed between the active semiconductor layer and the substrate material, and the bulk region being provided by the substrate material, an insulating structure formed in the hybrid substrate, the insulating structure separating the bulk region and the SOI region, and a gate electrode formed in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.

Some embodiments include an integrated structure having stacked conductive levels. At least some of the conductive levels are wordline levels and include control gate regions of memory cells. One of the conductive levels is a vertically outermost conductive level along an edge of the stack. Vertically-extending channel material is along the conductive levels. Some of the channel material extends along the memory cells. An extension region of the channel material is vertically outward of the vertically outermost conductive level. A charge-storage structure has a first region directly between the vertically outermost conductive level and the channel material, and has a second region which extends vertically outward of the vertically outermost conductive level and is along the extension region of the channel material.

An alternating stack of insulating layers and spacer material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. The spacer material layers are removed to form backside recesses. The backside recesses are sequentially filled with a continuous layer stack including a first continuous metallic nitride layer, a continuous tungsten layer, a second continuous metallic nitride layer, and a continuous metal fill layer. The continuous layer stack is patterned to form electrically conductive layers. Each electrically conductive layer includes a liner stack of a first metallic nitride liner, a tungsten liner, and a second metallic nitride liner. The liner stack is a diffusion barrier for high diffusivity species such as fluorine and boron.

Disclosed is a method of manufacturing a semiconductor device, including: forming a stacked structure including first material layers and second material layers alternately stacked on each other; forming a pillar passing through the stacked structure, the pillar including a protruding portion protruding above an uppermost surface of the stacked structure; forming a conductive layer surrounding the protruding portion of the pillar; and forming a conductive pattern in contact with the protruding portion of the pillar by oxidizing a surface of the conductive layer.