A semiconductor device includes a fin structure on a substrate and extending in a first direction, a gate electrode crossing over the fin structure, source/drain regions on the fin structure at opposite sides of the gate electrode, and a barrier layer between the fin structure and each of the source/drain regions. The fin structure includes a material having a lattice constant different from that of the substrate, the fin structure, the source/drain regions, and the barrier layer include germanium, and a germanium concentration in the barrier layer is greater than that in the fin structure and less than a maximum germanium concentration in each of the source/drain regions.

Device structures for a bipolar junction transistor and methods of fabricating a device structure for a bipolar junction transistor. A base layer comprised of a first semiconductor material is formed. An emitter layer comprised of a second semiconductor material is formed on the base layer. The emitter layer is patterned to form an emitter finger having a length and a width that changes along the length of the emitter finger.

A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.

Provided are an oxide semiconductor excellent in transparency, mobility, and weatherability, etc., and a semiconductor device having the oxide semiconductor, a p-type semiconductor being realizable in the oxide semiconductor. The oxide semiconductor consists of a composite oxide, which has a crystal structure including a pyrochlore structure, containing at least one or more kinds of elements selected from Nb and Ta, and containing Sn element, and its holes become charge carriers by the condition that Sn.sup.4+/(Sn.sup.2++Sn.sup.4+) which is a ratio of Sn.sup.4+ to a total amount of Sn in the composite oxide is 0.124≤Sn.sup.4+/(Sn.sup.2++Sn.sup.4+)≤0.148.

Semiconductor devices, fin field effect transistor (FinFET) devices, and methods of manufacturing semiconductor devices are disclosed. In some embodiments, a semiconductor device includes a substrate comprising a first fin and a second fin. A first epitaxial fin is disposed over the first fin, and a second epitaxial fin is disposed over the second fin. The second fin is proximate the first fin. The first epitaxial fin and the second epitaxial fin have an upper portion with a substantially pillar shape.

A lateral bipolar junction transistor including a base region on a dielectric substrate layer. The base region includes a layered stack of alternating material layers of a first lattice dimension semiconductor material and a second lattice dimension semiconductor material. The first lattice dimension semiconductor material is different from the second lattice dimension semiconductor material to provide a strained base region. A collector region is present on the dielectric substrate layer in contact with a first side of the base region. An emitter region is present on the dielectric substrate in contact with a second side of the base region that is opposite the first side of the base region.

A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of chamfer shorts, and the second DOE contains fill cells configured to enable NC detection of corner shorts. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured.

An embodiment includes a device comprising: a first epitaxial layer, coupled to a substrate, having a first lattice constant; a second epitaxial layer, on the first layer, having a second lattice constant; a third epitaxial layer, contacting an upper surface of the second layer, having a third lattice constant unequal to the second lattice constant; and an epitaxial device layer, on the third layer, including a channel region; wherein (a) the first layer is relaxed and includes defects, (b) the second layer is compressive strained and the third layer is tensile strained, and (c) the first, second, third, and device layers are all included in a trench. Other embodiments are described herein.

Methods for forming the fin field effect transistor (FinFET) device structure are provided. The method includes forming first fin structures and second fin structures on a first region and a second region of a substrate, respectively, and a number of the first fin structures is greater than a number of the second fin structures. The method also includes forming a sacrificial layer on the first fin structures and the second fin structures and performing an etching process to the sacrificial layer to form an isolation structure on the substrate.

Disclosed herein is a driver circuit including a first group of transistors provided between first and second nodes and including n of the transistor(s) where n is equal to or greater than one, and a second group of transistors provided in parallel with the first group of transistors and including m of the transistor(s) where m is equal to or greater than one and not equal to n, the m transistors being connected together in series. The n-channel transistor in the first group and at least one of the two n-channel transistors in the second group have their gate connected to an input node.