A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

A display device and a method for fabricating the same are provided. The display device comprises pixels connected to scan lines, and to data lines crossing the scan lines, each of the pixels including a light emitting element, and a first transistor configured to control a driving current supplied to the light emitting element according to a data voltage applied from the data line, the first transistor including a first active layer having an oxide semiconductor, and a first oxide layer on the first active layer and having a crystalline oxide containing tin (Sn).

A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of merged-via opens, and the second DOE contains fill cells configured to enable NC detection of snake opens. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured.

The present disclosure discloses a method for preparing an array substrate, an array substrate and a display panel, wherein the method comprises: forming a buffer layer on a substrate in a first region and a second region, wherein the buffer layer has a groove located in the second region; forming a first indium oxide thin film on the buffer layer in the first region; forming a second indium oxide thin film in the groove; performing a reduction process on the second indium oxide thin film to obtain indium particles; forming an amorphous silicon thin film in the groove, and inducing the amorphous silicon of the amorphous silicon thin film to form microcrystalline silicon at a preset temperature by using the indium particles; and removing the indium particles in the microcrystalline silicon to form a microcrystalline silicon semiconductor layer of the microcrystalline silicon thin film transistor.

Techniques are provided that can impart sufficient electrical conductivity to a semiconductor crystal exhibiting low doping efficiency for silicon atoms, such as InGaAs, by implanting only a small amount of silicon atoms. Such a semiconductor wafer may include a first semiconductor crystal layer, a second semiconductor crystal layer exhibiting a conductivity type that is different from the first layer, a third semiconductor crystal layer exhibiting the conductivity type of the first layer and having a larger band gap than the second semiconductor crystal layer, and a fourth semiconductor crystal layer exhibiting the conductivity type of the first layer and having a smaller band gap than the third semiconductor crystal layer. The fourth semiconductor crystal layer contains a first element that generates a first carrier of a corresponding conductivity type and a second element that generates a second carrier of a corresponding conductivity type.

Graphene nanoribbon arrays, methods of growing graphene nanoribbon arrays, and electronic and photonic devices incorporating the graphene nanoribbon arrays are provided. The graphene nanoribbons in the arrays are formed using a seed-mediated, bottom-up, chemical vapor deposition (CVD) technique in which the (001) facet of a semiconductor substrate and the orientation of the seed particles on the substrate are used to orient the graphene nanoribbon crystals preferentially along a single [110] direction of the substrate.

A field-effect transistor device and a method of isolating a field-effect transistor device. The method includes forming a layer of silicon germanium (SiGe) over a substrate, and fabricating a dummy gate stack above a silicon layer formed on the layer of SiGe. Etching the silicon layer defines a channel region below the dummy gate stack. The channel is isolated from the substrate by forming a cavity between the channel region and the substrate below the channel region, the cavity extending over a length of the channel region, wherein the length of the channel region extends from a source region to a drain region below the dummy gate stack. The cavity is filled with an oxide and a low K spacer material to isolate the channel region from the substrate.

Disclosed is a method of preparing a thin film transistor substrate, a thin film transistor substrate, and a display apparatus. The method includes forming a conductive material layer, forming a hydrophobic insulation layer on the conductive material layer, forming a photoresist layer on the hydrophobic insulation layer, patterning the photoresist layer to form a photoresist pattern, removing a segment in the hydrophobic insulation layer that is not covered by the photoresist pattern to form a hydrophobic insulation pattern, and removing a segment in the conductive material layer that is not covered by the hydrophobic insulation pattern to form a conductive pattern.

A highly reliable semiconductor device having a high on-state current is provided. The semiconductor device includes a first insulator, a second insulator over the first insulator, a first oxide over the first insulator, a second oxide over the first oxide, a first conductor and a second conductor over the second oxide, a third insulator over the first conductor, a fourth insulator over the second conductor, a third oxide over the second oxide, a fifth insulator over the third oxide, a third conductor that is positioned over the fifth insulator and overlaps with the third oxide, a sixth insulator covering the first to fifth insulators, the first oxide, the second oxide, and the first to third conductors, and a seventh insulator over the sixth insulator.

Provided is a shallow trench isolating structure and a semiconductor device. The trench isolating structure is formed in a substrate and includes a first and a second part. The first part has a first side wall extending from a surface of the substrate to a location, the first side wall has a first slope, and a surface of it has a first roughness. The second part has a second side wall extending from the first side wall to a location, the second side wall has a second slope, and a surface of it has a second roughness, the second slope is greater than the first slope, and the second roughness is greater than the first roughness. The disclosure solves the problem that it is difficult to fill the shallow trench isolating structure, and an undersized available space of the surface of the substrate may not be caused.