Provided is an interposer structure. The interposer structure comprises an interposer substrate, an interlayer insulating film which covers a top surface of the interposer substrate, a capacitor structure in the interlayer insulating film and a wiring structure including a first wiring pattern and a second wiring pattern spaced apart from the first wiring pattern, on the interlayer insulating film, wherein the capacitor structure includes an upper electrode connected to the first wiring pattern, a lower electrode connected to the second wiring pattern, and a capacitor dielectric film between the upper electrode and the lower electrode.

A liquid crystal display device with a high aperture ratio is provided. A liquid crystal display device with low power consumption is provided. A display device includes a transistor and a capacitor. The transistor includes a first insulating layer, a first semiconductor layer in contact with the first insulating layer, a second insulating layer in contact with the first semiconductor layer, and a first conductive layer electrically connected to the first semiconductor layer via an opening portion provided in the second insulating layer. The capacitor includes a second conductive layer in contact with the first insulating layer, the second insulating layer in contact with the second conductive layer, and the first conductive layer in contact with the second insulating layer. The second conductive layer includes a composition similar to that of the first semiconductor layer. The first conductive layer and the second conductive layer are configured to transmit visible light.

The present disclosure relates to an integrated chip. The integrated chip includes a source region and a drain region disposed within an upper surface of a substrate. One or more dielectric materials are disposed within a trench defined by sidewalls of the substrate that surround the source region and the drain region. The one or more dielectric materials include one or more interior surfaces defining a recess within the one or more dielectric materials. A gate structure is disposed over the substrate between the source region and the drain region. The gate structure includes a first gate material over the upper surface of the substrate and a second gate material. The second gate material completely fills the recess as viewed along a cross-sectional view.

Disclosed herein is a polymeric film, the film comprising a polymeric matrix material, a plurality of perovskite nanocrystals and/or aggregates of perovskite nanocrystals dispersed throughout the polymeric matrix material. There is also disclosed a perovskite polymer resin composition, a perovskite-polymer resin composition, a perovskite ink and a method of forming a luminescent film using any one of the compositions or ink. Preferably, the perovskite material is a lead halide perovskite containing a cation selected from Cs, an alkylammonium ion, or a formamidinium ion. The polymeric matrix is preferably formed from monomers comprising a vinyl or an acrylate group.

Disclosed herein is a polymeric film, the film comprising a polymeric matrix material, a plurality of perovskite nanocrystals and/or aggregates of perovskite nanocrystals dispersed throughout the polymeric matrix material. There is also disclosed a perovskite polymer resin composition, a perovskite-polymer resin composition, a perovskite ink and a method of forming a luminescent film using any one of the compositions or ink. Preferably, the perovskite material is a lead halide perovskite containing a cation selected from Cs, an alkylammonium ion, or a formamidinium ion. The polymeric matrix is preferably formed from monomers comprising a vinyl or an acrylate group.

A thin film transistor includes at least a gate electrode, a gate insulating film, an oxide semiconductor layer, source/drain electrodes, and at least one layer of a passivation film on a substrate. Metal elements constituting the oxide semiconductor layer include In, Ga, Zn, and Sn. Respective ratios of the metal elements to a total (In+Ga+Zn+Sn) of the metal elements in the oxide semiconductor layer satisfy: In: 30 atom % or more and 45 atom % or less, Ga: 5 atom % or more and less than 20 atom %, Zn: 30 atom % or more and 60 atom % or less, and Sn: 4.0 atom % or more and less than 9.0 atom %.

A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

A display device may include a first gate electrode disposed on a substrate, a buffer layer disposed on the first gate electrode, a first active pattern on the buffer layer, the first active pattern overlapping the first gate electrode and including an oxide semiconductor, a second active pattern on the buffer layer, spaced apart from the first active pattern, and including an oxide semiconductor, the second active pattern including a channel region, and a source region and a drain region, a source pattern and a drain pattern respectively at ends of the first active pattern, a first insulation pattern disposed on the first active pattern, a second insulation pattern disposed on the channel region, a first oxygen supply pattern on the first insulation pattern, a second oxygen supply pattern on the second insulation pattern, and a second gate electrode on the second oxygen supply pattern.

A semiconductor device includes: a substrate including an active region and a device isolation region; a flat plate structure formed on the substrate; an oxide semiconductor layer covering a top surface of the flat plate structure and continuously arranged on a top surface of the substrate in the active region and the device isolation region; a gate structure arranged on the oxide semiconductor layer and including a gate dielectric layer and a gate electrode; and a source/drain region arranged on both sides of the gate structure and formed in the oxide semiconductor layer, in which, when viewed from a side cross-section, an extending direction of the flat plate structure and an extending direction of the gate structure cross each other.

A semiconductor package is provided. The semiconductor package includes a semiconductor die, a stack of polymer layers, redistribution elements and a passive filter. The polymer layers cover a front surface of the semiconductor die. The redistribution elements and the passive filter are disposed in the stack of polymer layers. The passive filter includes a ground plane and conductive patches. The ground plane is overlapped with the conductive patches, and the conductive patches are laterally separated from one another. The ground plane is electrically coupled to a reference voltage. The conductive patches are electrically connected to the ground plane, electrically floated, or electrically coupled to a direct current (DC) voltage.