The present disclosure provides a method for manufacturing a semiconductor structure, including patterning a photo-sensitive polymer layer with a plurality of trenches by a first mask, the first mask having a first line pitch, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, the second mask having a second line pitch, the first mask and the second mask having substantially identical pattern topography, and the second line pitch being greater than the first line pitch, and selectively plating conductive material in the plurality of trenches.

A discrete capacitor of the present invention includes a substrate having a front surface portion, an impurity diffusion layer formed on the front surface portion of the substrate, an oxide film formed on the substrate and having a first opening to selectively expose the impurity diffusion layer, a dielectric film formed on the impurity region having been exposed from the oxide film, and a first electrode opposed to the impurity diffusion layer with the dielectric film therebetween, wherein the impurity concentration on the front surface portion of the impurity diffusion layer is 5×10.sup.19 cm.sup.−3 or more.

A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.

In one aspect, a method of fabricating a transistor includes depositing a first epitaxial layer, depositing a second epitaxial layer on the first epitaxial layer, implanting the second epitaxial layer to form a p-field termination region, depositing a third epitaxial layer on the p-field termination layer and forming trenches in the third epitaxial layer. The trenches include a trench gate of the transistor and a termination trench.

The present invention provides a structure for integrating microfluidic devices and electrical biosensors, including: a substrate for carrying an electrical biosensor; a microfluidic channel layer for providing at least a fluid to flow; a cover member for the inflow and outflow of the at least a fluid, and an electrical biosensor, having a biosensing layer and mounted to the cover member in a flip-chip manner; wherein the fluid flows into an inlet, passes the electrical biosensor for sensing and flows out through a fluid outlet.

A laterally diffused metal oxide semiconductor (LDMOS) device that may include an oxide region that comprises a bottom surface; a drain that is positioned between a left drift region and a right drift region and below the bottom surface; wherein the oxide region further comprises a first sloped surface and a second sloped surface; wherein a first angle between the first sloped surface and the bottom surface does not exceed twenty degrees; and wherein a second angle between the second sloped surface and the bottom surface of the oxide region does not exceed twenty degrees.

An interposer for an integrated circuit includes a first side and a second side. The interposer includes a substrate and a via disposed in the substrate. A first electrical contact is disposed on the first side. A second electrical contact is disposed on the second side and electrically connected to the via. The interposer also includes a multiple-time programmable (“MTP”) element electrically connected to the first electrical contact and/or the via.

Fully integrated, on-chip DC-DC power converters are provided. In one aspect, a DC-DC power converter includes: a SOI wafer having a SOI layer separated from a substrate by a buried insulator, wherein the SOI layer and the buried insulator are selectively removed from at least one first portion of the SOI wafer, and wherein the SOI layer and the buried insulator remain present in at least one second portion of the SOI wafer; at least one GaN transistor formed on the substrate in the first portion of the SOI wafer; at least one CMOS transistor formed on the SOI layer in the second portion of the SOI wafer; a dielectric covering the GaN and CMOS transistors; and at least one magnetic inductor formed on the dielectric. A method of forming a fully integrated DC-DC power converter is also provided.

A semiconductor device and method of manufacturing the same are provided. In one embodiment, method includes forming a first oxide layer over a substrate, forming a silicon-rich, oxygen-rich, oxynitride layer on the first oxide layer, forming a silicon-rich, nitrogen-rich, and oxygen-lean nitride layer over the oxynitride layer, and forming a second oxide layer on the nitride layer. Generally, the nitride layer includes a majority of charge traps distributed in the oxynitride layer and the nitride layer. Optionally, the method further includes forming a middle oxide layer between the oxynitride layer and the nitride layer. Other embodiments are also described.

A capacitor includes a first electrode, a second electrode, and a dielectric layer of molecular material disposed between said first and second electrodes. The molecular material is described by the general formula:

D.sub.p-(Core)- H.sub.q,

where Core is a polarizable conductive anisometric core, having conjugated π-systems, and characterized by a longitudinal axis, D and H are insulating substituents, and p and q are numbers of the D and H substituents accordingly. And Core possesses at least one dopant group that enhances polarizability.