An array substrate includes a glass substrate GS, an alignment mark 29, and first traces 19. The glass substrate GS has a corner portion 30 having an outline defined by a first edge portion 11b1 and a second edge portion 11b2 crossing the first edge portion 11b1. The alignment mark 29 is disposed at the corner portion 30 and used as the positioning index in mounting a driver 21 and a flexible printed circuit board 13. The alignment mark 29 at least includes first and second side portions 29a, 29b parallel to the first and second edge portions 11b1, 11b2, respectively. One end of the second side portion 29b is continuous to one end of the first side portion 29a. The alignment mark 29 has an outline that is on a same plane with a reference line BL connecting other ends of the first side portion 29a and the second side portion 29b linearly. The first traces 19 include inclined portions 31 that are inclined with respect to the first and second side portions 29a, 29b along the reference line BL.

An array substrate includes a glass substrate GS, an alignment mark 29, and first traces 19. The glass substrate GS has a corner portion 30 having an outline defined by a first edge portion 11b1 and a second edge portion 11b2 crossing the first edge portion 11b1. The alignment mark 29 is disposed at the corner portion 30 and used as the positioning index in mounting a driver 21 and a flexible printed circuit board 13. The alignment mark 29 at least includes first and second side portions 29a, 29b parallel to the first and second edge portions 11b1, 11b2, respectively. One end of the second side portion 29b is continuous to one end of the first side portion 29a. The alignment mark 29 has an outline that is on a same plane with a reference line BL connecting other ends of the first side portion 29a and the second side portion 29b linearly. The first traces 19 include inclined portions 31 that are inclined with respect to the first and second side portions 29a, 29b along the reference line BL.

The purpose of the present invention is to improve the pressure resistance of a cavity in a semiconductor sensor device employing a resin package, and to do so without adversely affecting the embeddability of an electrically conductive member. The semiconductor sensor device has a gap 1a sealed in an airtight manner inside a laminate structure of a plurality of laminated substrates 1, 4, and 5, and has a structure in which the outside of the laminate structure is covered by a resin, wherein a platy component 2 having at least one side that is greater in length than the length of one side of the gap 1a along this side is arranged to the outside of an upper wall 1b of the gap 1, the upper wall 1b of the gap being mechanically suspended by the platy component 2.

The purpose of the present invention is to improve the pressure resistance of a cavity in a semiconductor sensor device employing a resin package, and to do so without adversely affecting the embeddability of an electrically conductive member. The semiconductor sensor device has a gap 1a sealed in an airtight manner inside a laminate structure of a plurality of laminated substrates 1, 4, and 5, and has a structure in which the outside of the laminate structure is covered by a resin, wherein a platy component 2 having at least one side that is greater in length than the length of one side of the gap 1a along this side is arranged to the outside of an upper wall 1b of the gap 1, the upper wall 1b of the gap being mechanically suspended by the platy component 2.

A method is provided. The method includes one or more of extracting a die from an original packaged integrated circuit, modifying the extracted die, reconditioning the modified extracted die, placing the reconditioned die into a cavity of a hermetic package base, bonding a plurality of bond wires between reconditioned die pads of the reconditioned die to leads of the hermetic package base or downbonds to create an assembled hermetic package base, and sealing a hermetic package lid to the assembled hermetic package base to create a new packaged integrated circuit. Modifying the extracted die includes removing the one or more ball bonds on the one or more die pads. Reconditioning the modified extracted die includes adding a sequence of metallic layers to bare die pads of the modified extracted die. The extracted die is a fully functional semiconductor die with one or more ball bonds on one or more die pads of the extracted die.

A method is provided. The method includes one or more of extracting a die from an original packaged integrated circuit, modifying the extracted die, reconditioning the modified extracted die, placing the reconditioned die into a cavity of a hermetic package base, bonding a plurality of bond wires between reconditioned die pads of the reconditioned die to leads of the hermetic package base or downbonds to create an assembled hermetic package base, and sealing a hermetic package lid to the assembled hermetic package base to create a new packaged integrated circuit. Modifying the extracted die includes removing the one or more ball bonds on the one or more die pads. Reconditioning the modified extracted die includes adding a sequence of metallic layers to bare die pads of the modified extracted die. The extracted die is a fully functional semiconductor die with one or more ball bonds on one or more die pads of the extracted die.

A power module includes a base plate, first, second, and third semiconductor chips. At least one of a third edge or fourth edge of the first semiconductor chip is disposed adjacent to a side end of the base plate. Among a half of a distance from a first edge of the first semiconductor chip to one edge of the second semiconductor chip, a half of a distance from a second edge of the first semiconductor chip to one edge of the third semiconductor chip, and a distance from the third edge or fourth edge of the first semiconductor chip disposed adjacent to the side end of the base plate to the side end of the base plate, a length of a solder fillet formed on the edge of the first semiconductor chip at the shortest distance is formed in the shortest length.

In a semiconductor device, a thinly-molded portion covering a whole of a heat dissipating surface portion of a lead frame and a die pad space filled portion are integrally molded from a second mold resin, because of which adhesion between the thinly-molded portion and lead frame improves owing to the die pad space filled portion adhering to a side surface of the lead frame. Also, as the thinly-molded portion is partially thicker owing to the die pad space filled portion, strength of the thinly-molded portion increases, and a deficiency or cracking is unlikely to occur.

In a semiconductor device, a thinly-molded portion covering a whole of a heat dissipating surface portion of a lead frame and a die pad space filled portion are integrally molded from a second mold resin, because of which adhesion between the thinly-molded portion and lead frame improves owing to the die pad space filled portion adhering to a side surface of the lead frame. Also, as the thinly-molded portion is partially thicker owing to the die pad space filled portion, strength of the thinly-molded portion increases, and a deficiency or cracking is unlikely to occur.

A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode.