Disclosed is a chip-to-chip interface using a microstrip circuit and a dielectric waveguide. A board-to-board interconnection device, according to one embodiment of the present invention, comprises: a waveguide which has a metal cladding and transmits a signal from a transmitter-side board to a receiver-side board; and a microstrip circuit which is connected to the waveguide and has a microstrip-to-waveguide transition (MWT), wherein the microstrip circuit matches a microstrip line and the waveguide, adjusts the bandwidth of a predetermined first frequency band among the frequency bands of the signal, and provides same to the receiver.

Disclosed is a chip-to-chip interface using a microstrip circuit and a dielectric waveguide. A board-to-board interconnection device, according to one embodiment of the present invention, comprises: a waveguide which has a metal cladding and transmits a signal from a transmitter-side board to a receiver-side board; and a microstrip circuit which is connected to the waveguide and has a microstrip-to-waveguide transition (MWT), wherein the microstrip circuit matches a microstrip line and the waveguide, adjusts the bandwidth of a predetermined first frequency band among the frequency bands of the signal, and provides same to the receiver.

A substrate includes, two first through-holes to which high-frequency signals are transmitted and which are arranged side by side so as to have a predetermined distance, and at least three reference potential second through-holes arranged side by side so as to have an distance smaller than the predetermined distance with respect to the two first through-holes. Among three of the second through-holes, one of the second through-holes is arranged in a region between the two first through-holes, and other two of the second through-holes are arranged in a region other than the region between the first through-holes such that one of the other two second through-holes is arranged side by side with respect to one of the two first through-holes, and the other of other two second through-holes is arranged side by side with respect to the other of the two first through-holes.

A balun including first and second conductive tracks located vertically in line and at a distance from each other and having a same pattern.

The accuracy of an impedance tuner may be improved and the size may be reduced by using linear actuators instead of rotary motors. The linear actuator may be integrated with position sensors to allow very small size, and implemented with a servo system for best accuracy and speed. Spring loaded arms holding the mismatch probes allow the tuner to operate in any orientation to further fit into small spaces. The small size reduces losses by allowing direct connection to wafer probes for on-wafer measurement systems.

The accuracy of an impedance tuner may be improved and the size may be reduced by using linear actuators instead of rotary motors. The linear actuator may be integrated with position sensors to allow very small size, and implemented with a servo system for best accuracy and speed. Spring loaded arms holding the mismatch probes allow the tuner to operate in any orientation to further fit into small spaces. The small size reduces losses by allowing direct connection to wafer probes for on-wafer measurement systems.

Described is a frequency selective limiter (FSL) module comprising a cascade of an FSL and a functional limiter (e.g. a conventional semiconductor limiter comprising a PIN diode) with steady state limiting and power threshold values selected such the FSL module provides suppression of a spike leakage power and while still enabling frequency selective limiting.

Described is a frequency selective limiter (FSL) module comprising a cascade of an FSL and a functional limiter (e.g. a conventional semiconductor limiter comprising a PIN diode) with steady state limiting and power threshold values selected such the FSL module provides suppression of a spike leakage power and while still enabling frequency selective limiting.

A routing structure of a two-core parallel shielded electric wire includes: two insulated electric wires that are arranged in parallel; and a shield layer that is attached around the two insulated electric wires and extends in a longitudinal direction of the two insulated electric wires. In the routing structure, the two-core parallel shielded electric wire is rerouted by bent twisting the two-core parallel shielded electric wire in a short axis direction at a route change point along a long axis direction of the two-core parallel shielded electric wire, and the number of bent twisted points in the short axis direction is 1.43 or less per meter.

A routing structure of a two-core parallel shielded electric wire includes: two insulated electric wires that are arranged in parallel; and a shield layer that is attached around the two insulated electric wires and extends in a longitudinal direction of the two insulated electric wires. In the routing structure, the two-core parallel shielded electric wire is rerouted by bent twisting the two-core parallel shielded electric wire in a short axis direction at a route change point along a long axis direction of the two-core parallel shielded electric wire, and the number of bent twisted points in the short axis direction is 1.43 or less per meter.