Patent classifications
H02H9/00
DC interrupting device
In order to provide a DC interrupting device that does not easily cause erroneous melting of current-limiting fuses at normal times with no fault current, and that can also deliver good current-limiting performance at the time of occurrence of fault current, the DC interrupting device includes: a (k−1)th current path including a (k−1)th current-limiting fuse, where k is an integer of not less than two and not more than N, and N is an integer of not less than two; and a kth current path connected in parallel to the (k−1)th current path and including a kth current-limiting fuse. The inductance value of the inductance component of the kth current path is higher than the inductance value of the inductance component of the (k−1)th current path.
DC interrupting device
In order to provide a DC interrupting device that does not easily cause erroneous melting of current-limiting fuses at normal times with no fault current, and that can also deliver good current-limiting performance at the time of occurrence of fault current, the DC interrupting device includes: a (k−1)th current path including a (k−1)th current-limiting fuse, where k is an integer of not less than two and not more than N, and N is an integer of not less than two; and a kth current path connected in parallel to the (k−1)th current path and including a kth current-limiting fuse. The inductance value of the inductance component of the kth current path is higher than the inductance value of the inductance component of the (k−1)th current path.
Transient power management circuit
An electronic device can include a battery bus, a load having a transient power requirement, and a transient power management circuit coupled between the battery bus and the load and configured to meet the transient instantaneous power requirement of the load while maintaining a minimum voltage on the battery bus. The transient power management circuit can include a boost converter coupled between the battery bus and a capacitor bank, and the load may be coupled to the capacitor bank. A control circuit may be configured to operate the boost converter to charge the capacitor bank. A control switch may be coupled between the boost converter and the capacitor bank, and the control circuit may be further configured to limit inrush current into the capacitor bank. Additionally, a state of charge of the battery may be estimated from a time required to charge the capacitor bank.
Controlled three-pole close for transformers
An intelligent electronic device (IED) may obtain a residual flux of each phase of a transformer. The IED may determine a maximum difference (DIF) signal based on the residual flux and the prospective flux associated with potential close POWs of the corresponding phase. The TED may select a closing POW that results in a minimum DIF signal. The TED may send a signal to close a ganged switching device of the transformer at a time based on the selected closing POW.
DC-DC converter with output-side storage capacitor arrangement
A DC-DC converter includes an output-side storage capacitor arrangement which has a parallel circuit formed of an electrolytic capacitor, a ceramic capacitor and a circuit arrangement. The circuit arrangement has a series circuit formed of a hybrid electrolytic capacitor and a suppressor diode as well as a resistance connected in parallel with the hybrid electrolytic capacitor.
DC-DC converter with output-side storage capacitor arrangement
A DC-DC converter includes an output-side storage capacitor arrangement which has a parallel circuit formed of an electrolytic capacitor, a ceramic capacitor and a circuit arrangement. The circuit arrangement has a series circuit formed of a hybrid electrolytic capacitor and a suppressor diode as well as a resistance connected in parallel with the hybrid electrolytic capacitor.
Power sourcing equipment and power over ethernet system
Power sourcing equipment for power over Ethernet (PoE) includes a power supply control circuit, an Ethernet port, and a surge protection circuit. The surge protection circuit includes a first circuit, a second circuit, and a common discharge circuit. The first circuit is connected to a power supply pin group of the Ethernet port, the power supply control circuit, and the common discharge circuit. The second circuit is connected to a non-power supply pin group of the Ethernet port and the common discharge circuit. The first circuit transmits, to the common discharge circuit, a first surge that is input from the power supply pin group. The second circuit transmits, to the common discharge circuit, a second surge that is input from the non-power supply pin group. The common discharge circuit discharges the first surge and the second surge to ground.
Power sourcing equipment and power over ethernet system
Power sourcing equipment for power over Ethernet (PoE) includes a power supply control circuit, an Ethernet port, and a surge protection circuit. The surge protection circuit includes a first circuit, a second circuit, and a common discharge circuit. The first circuit is connected to a power supply pin group of the Ethernet port, the power supply control circuit, and the common discharge circuit. The second circuit is connected to a non-power supply pin group of the Ethernet port and the common discharge circuit. The first circuit transmits, to the common discharge circuit, a first surge that is input from the power supply pin group. The second circuit transmits, to the common discharge circuit, a second surge that is input from the non-power supply pin group. The common discharge circuit discharges the first surge and the second surge to ground.
Three dimensional integrated circuit electrostatic discharge protection and prevention test interface
The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.
Electrical contact thermal sensing system and method
A thermal sensing system includes an electrical contact, a sensing element, and at least one position sensor. The electrical contact releasably connects to a mating contact for establishing a conductive path across a mating interface. The electrical contact defines a channel therein that extends from an opening along an outer surface of the electrical contact. The sensing element is at least partially outside of the channel and is configured to move relative to the electrical contact from a first position to a second position based on a temperature increase within the channel that exceeds a designated threshold temperature. The at least one position sensor is spaced apart from the electrical contact and is configured to detect a position change of the sensing element from the first position to the second position, indicating that the temperature within the channel exceeds the designated threshold temperature.