A power supply circuit for a switching mode power supply, having: a charging capacitor coupled to an auxiliary winding; a power supply diode coupled to a power supply capacitor, wherein the charging capacitor has a connecting terminal coupled to the power supply diode, and the charging capacitor and the power supply diode are serially coupled between the auxiliary winding of the switching mode power supply and the power supply capacitor; and a power supply switch coupled between the connecting terminal and a primary ground of the switching mode power supply.

A deadtime control scheme for improving buck converter light load efficiency.

A system including an arc flash sensor that detects an arc flash event and an arc flash mitigation device in communication with the sensor. The mitigation device includes a path of least resistance having a path input and a path output. The arc flash sensor is located downstream the output. The mitigation device includes an electro-mechanical switch between the input and the output and an actuator. The mitigation device also includes a bypass power switch device that includes a solid-state circuit interrupter and that conduct current between the input and the output in response to an open-circuit condition of the switch. A system controller is provided to generate a trigger to activate the actuator to generate the open-circuit condition of the switch, which causes the power switch device to interrupt a fault current associated with a fault event in response to detection of the arc flash event.

An MMC-type power conversion device includes a failure detection unit that detects presence or absence of failure of each of n upper arm current detectors and n lower arm current detectors. The failure detection unit makes a first determination based on comparison between a sum of detection values of n upper arm current detectors and the sum of detection values of n lower arm current detectors, a second determination based on comparison between a current command value and the sum of detection values of n upper arm current detectors, a third determination based on comparison between a current command value and the sum of detection values of n lower arm current detectors, and a fourth determination of comparing, for each phase, the sum of detection values of the current detectors of an upper arm and a lower arm of the same phase.

A circuit assembly for connection to a current source, preferably a 4-20 mA current loop and/or a high-impedance voltage source, preferably a high-impedance voltage source comprising an internal resistance greater than or equal to 100 ohms, includes at least one boost converter with a coil, a diode, in particular a flyback diode, which is connected in series with the coil, an output-side storage capacitor for summing an output voltage, and a switching element for connecting the coil to ground; a circuit part for dynamically controlling the switching element of the boost converter, wherein the circuit part is at least designed to control the switching element of the boost converter in a start-up phase such that the current source directly charges the storage capacitor via the coil until a predefinable reference value is reached.

A control circuit for controlling a stackable multiphase power converter includes: a synchronization terminal; a synchronization signal connected to the synchronization terminals of a plurality of the control circuits in parallel, wherein the synchronization signal includes a plurality of pulses to be successively counted as a count number; and a reset signal, configured to reset and initiate the count number; wherein the control circuit further comprises a phase-sequence number, wherein the control circuit enables a corresponding power stage circuit to generate a phase of the output power when the count number reaches the phase-sequence number.

In described examples, an integrated circuit (IC) includes an isolation, an input/output (IO), and a low power mode (LPM) control logic. The isolation includes a level shift with pull-down configured to weakly pull down the voltage of signals that travel through the isolation. The IO includes an input and a physical connector for coupling to a power management IC. The IO provides an asserted-low LPM enable signal to the physical connector in response to the IO input. An output of the LPM control logic is coupled via the isolation to the input of the IO. The LPM control logic provides a high voltage signal to the input of the IO as a default during power on reset (POR) of the IC. The pull-down pulls the LPM enable signal voltage to the asserted low voltage in response to a voltage of the LPM enable signal falling below a threshold.

A conversion control circuit controls a power stage circuit of a switching power converter according to a first feedback signal and a second feedback signal, wherein the conversion control circuit includes an error amplifier circuit, a ramp signal generation circuit, a pulse width modulation circuit, and a quick response control circuit. The quick response control circuit performs a quick response control function, wherein the quick response control function includes: comparing the second feedback signal with at least one reference threshold to generate a quick response control signal; and when the second feedback signal crosses the reference threshold, adjusting a slope of a ramp signal according to the quick response control signal to accelerate an increase or decrease of the duty of a PWM signal, thereby accelerating the transient response of the switching power converter.

A dual multi-level inverter topology with reduced switch count and small DC-link capacitor is provided. The inverter topology provides multi-level inverter operation without requiring a neutral point connection that is commonly present in a stacked capacitor topology (for example, a topology including two capacitors).

A constant on time converter control circuit and a constant on time converter are provided. The constant on time converter control circuit comprises an error amplifier, a voltage to current converter, and an initial current source. The error amplifier is for receiving a reference voltage signal and a feedback voltage signal and outputting a compensated voltage signal. The voltage to current converter receives the compensated voltage signal and outputs a converted current signal. The initial current source provides an initial current signal. The initial current signal and the converted current signal form a new reference voltage signal. A constant on time OFF time comparator receives the new reference voltage signal and the feedback voltage signal and outputs a control signal. The control signal affects the turning on and turning off of electronic switches to produce an output voltage of a constant on time converter.