Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

A memory system in an embodiment includes; one or more memory chips; and a controller connected to the one or more memory chips, the controller including a first driver configured to send a sending signal to the one or more memory chips, a second driver configured to generate a boost signal that is added to the sending signal, and a control circuit configured to set an addition period for the boost signal based on information relevant to a characteristic of distortion that occurs in the sending signal to the one or more memory chips.

This invention provides a resistance-adjustable means using at a pull-up driver and/or a pull-down driver of an OCD circuit. When the resistance-adjustable means is applicable to the pull-up driver, the resistance-adjustable means includes a triode-mode PMOS coupled to a circuit of the pull-up driver and at least one of one or more adjustable resistors and/or a fixed resistor, which are connected in series and coupled to the triode-mode PMOS, and the at least one of the adjustable resistors or the fixed resistor is coupled to an IO (input/output) pad. When the resistance-adjustable means is applicable to the pull-down driver, a triode-mode NMOS is used to replace the triode-mode PMOS for the resistance-adjustable means.

This application relates to methods and apparatus for driving a transducer with switching drivers where the switching driver has an output bridge stage for switching an output node between switching voltages and a modulator for controlling the duty cycle of the output bridge stage based on an input signal. The switching driver also includes a voltage controller for providing the switching voltages which is operable to provide different switching voltages in different driver modes. A controller is provided to control the driver mode of operation and the duty cycle of the switching driver based on the input signal, and the controller is configured to transition from a present driver mode to a new driver mode by controlling the voltage controller to provide the switching voltages for the new mode and controlling the modulator to vary the duty cycle of the output bridge stage. The change in duty cycle is controlled such that there is no substantial discontinuity in switching ripple due to the mode transition.

A terahertz element of an aspect of the present disclosure includes a semiconductor substrate, first and second conductive layers, and an active element. The first and second conductive layers are on the substrate and mutually insulated. The active element is on the substrate and electrically connected to the first and second conductive layers. The first conductive layer includes a first antenna part extending along a first direction, a first capacitor part offset from the active element in a second direction as viewed in a thickness direction of the substrate, and a first conductive part connected to the first capacitor part. The second direction is perpendicular to the thickness direction and first direction. The second conductive layer includes a second capacitor part, stacked over and insulated from the first capacitor part. The substrate includes a part exposed from the first and second capacitor parts. The first conductive part has a portion spaced apart from the first antenna part in the second direction with the exposed part therebetween as viewed in the thickness direction.

A filter includes multiple filter circuits. The filter circuits are coupled in series between an input terminal and an output terminal, to generate an output signal according to an input signal. One of the filter circuits operates as an active filter circuit or a passive filter circuit according to amplitude of the input signal.

An oscillator assembly includes a scribe seal, an oscillator circuit, and a calibration circuit. The oscillator circuit includes an output. The calibration circuit is coupled to the oscillator circuit. The calibration circuit includes a reference frequency terminal, a conductor coupled to the reference frequency terminal, and an oscillator input terminal. The conductor extends to an edge of the oscillator circuit assembly and penetrates the scribe seal. The oscillator input terminal is coupled to the output of the oscillator circuit.

An oscillator assembly includes a scribe seal, an oscillator circuit, and a calibration circuit. The oscillator circuit includes an output. The calibration circuit is coupled to the oscillator circuit. The calibration circuit includes a reference frequency terminal, a conductor coupled to the reference frequency terminal, and an oscillator input terminal. The conductor extends to an edge of the oscillator circuit assembly and penetrates the scribe seal. The oscillator input terminal is coupled to the output of the oscillator circuit.

A driving circuit includes: a primary driving module configured to receive a first signal and generate a second signal based on the first signal, driving capability of the second signal being greater than that of the first signal; and an auxiliary driving module connected to an output terminal of the primary driving module and configured to receive the first signal and generate an auxiliary driving signal based on the first signal, the auxiliary driving signal being configured to shorten a rise time of the second signal.