An apparatus for performing a frequency multiplication of an mm-wave wave signal is provided. The apparatus includes a first differential circuit that is capable of receiving a 0 phase component of an input signal and a 180 phase component of the input signal having a first frequency. The first differential circuit provides a first output signal that is twice the frequency and is in phase(0) based on the 0 the 180 phase components of the input signal. The apparatus also includes a second differential circuit that is capable of receiving a 90 phase component of the input signal and a 270 phase component of the input signal, and provide a first output signal that is twice the frequency and out of phase(180). The apparatus also includes a differential transformer that is configured to receive the first output signal and the second output signal. The differential transformer is configured to provide a differential output signal that has a second frequency that is twice the first frequency.

A digitalization device includes a first pulse delay unit, a second pulse delay unit, and an addition output unit. The first pulse delay unit includes (2.sup.n(2m1)) first delay units connected in series, and outputs a first signal according to the number of first delay units through which a first pulse signal passes. The second pulse delay unit includes (2.sup.n+(2m1)) second delay units connected in series, and outputs a second signal according to the number of the second delay units through which a second pulse signal passes. Here, n and m are natural numbers, and nm. The addition output unit outputs, as a digital value, an addition value obtained by adding a numerical value based on the output of the first pulse delay unit and a numerical value based on the output of the second pulse delay unit.

One illustrative dual mode frequency multiplier embodiment includes: a first and a second nonlinear element, a summation node, and a switchable phase shifter. The first and second nonlinear elements are driven by a differential signal to produce a first and a second branch signal each having even and odd harmonics, the even harmonics being in-phase and the odd harmonics being out of phase. The first and second branch signals combine at the summation node to form a combined signal. The switchable phase shifter couples the first nonlinear element to the summation node, providing the first branch signal with a phase shift switchable between 0 and 180 to suppress either the odd or the even harmonics from the combined signal.

A carrier recovery system for a receiver of a phase-modulated signal N-PSK, the system including a first pre-conditioning circuit of the signal received (S(t)), with the pre-conditioned signal (SP(t)) having a component, non-modulated in phase, at the frequency N.sub.c where .sub.c is the carrier used for the modulation N-PSK, and a carrier regeneration circuit to regenerate two sinusoidal signals in quadrature at the frequency .sub.c, with these signals being phase locked with respect to said non-modulated component in phase of the pre-conditioned signal.

An apparatus for performing a frequency multiplication of an mm-wave wave signal is provided. The apparatus includes a first differential circuit that is capable of receiving a 0 phase component of an input signal and a 180 phase component of the input signal having a first frequency. The first differential circuit provides a first output signal that is twice the frequency and is in phase(0) based on the 0 the 180 phase components of the input signal. The apparatus also includes a second differential circuit that is capable of receiving a 90 phase component of the input signal and a 270 phase component of the input signal, and provide a first output signal that is twice the frequency and out of phase(180). The apparatus also includes a differential transformer that is configured to receive the first output signal and the second output signal. The differential transformer is configured to provide a differential output signal that has a second frequency that is twice the first frequency.

A phase-variable frequency multiplier includes: a 90-degree divider for dividing an input signal into an I-signal and a Q-signal; an amplitude setting circuit for distributing each of the I-signal and the Q-signal to two paths, setting amplitudes of two of four signals including the two distributed I-signals and the two distributed Q-signals depending on a phase shift amount of the input signal, and outputting as set signals, the four signals including the signals with the set amplitudes; a first mixer for multiplying one of the two I-signals included in the set signals by one of the two Q-signals included in the set signals to generate a first signal having a frequency being twice the frequency of the input signal; a second mixer for multiplying the other of the two I-signals included in the set signals by the other of the two Q-signals included in the set signals to generate a second signal with an amplitude ratio with respect to the first signal, being a tangent or a reciprocal of a tangent of the phase shift amount and with a frequency being twice the frequency of the input signal; and a 90-degree combiner for applying a phase difference of 90 degrees between the first signal and the second signal, and combining the first signal having the phase difference of 90 degrees from the second signal with the second signal.

Apparatuses and Methods for dynamic adjustment of operating conditions of integrated circuits are provided. The method includes receiving, from a voltage reference module, an operating voltage of the integrated circuit, receiving a reference clock to be used as an operating frequency of the integrated circuit and is distributed to by the plurality of circuit blocks in the integrated circuit, measuring feedback path timing information of one or more circuit blocks in the plurality of circuit blocks, comparing the feedback path timing information of the one or more circuit blocks to the reference clock, determining timing margins of corresponding one or more feedback paths of the one or more circuit blocks based on the comparison, and generating a feedback for adjusting the operating voltage or the operating frequency of the integrated circuit based on the timing margins of the one or more feedback paths of the one or more circuit blocks.

A digitalization device includes a first pulse delay unit, a second pulse delay unit, and an addition output unit. The first pulse delay unit includes first delay units connected in series by (2.sup.n-(2m1)), and outputs a first signal according to the number of first delay units through which a first pulse signal passes. The second pulse delay unit includes second delay units connected in series by (2.sup.n+(2m1)), and outputs a second signal according to the number of the second delay units through which a second pulse signal passes. Here, n and m are natural numbers, and nm. The addition output unit outputs, as a digital value, an addition value obtained by adding a numerical value based on the output of the first pulse delay unit and a numerical value based on the output of the second pulse delay unit.

A local oscillator generation system includes a first frequency divider configured to divide frequencies of a first voltage controlled oscillator signal and a second voltage controlled oscillator signal by 2, and output a first divided signal and a second divided signal; a mixer configured to mix the first voltage controlled oscillator signal, the second voltage controlled oscillator signal, the first divided signal, and the second divided signal, and output a first frequency mixed signal and a second frequency mixed signal; a transimpedance amplifier configured to amplify the first frequency mixed signal and the second frequency mixed signal, and output a first amplified signal and a second amplified signal; and a band-pass filter configured to filter the first amplified signal and the second amplified signal, and output a first filtered signal and a second amplified signal.

A local oscillator generation system includes a first frequency divider configured to divide frequencies of a first voltage controlled oscillator signal and a second voltage controlled oscillator signal by 2, and output a first divided signal and a second divided signal; a mixer configured to mix the first voltage controlled oscillator signal, the second voltage controlled oscillator signal, the first divided signal, and the second divided signal, and output a first frequency mixed signal and a second frequency mixed signal; a transimpedance amplifier configured to amplify the first frequency mixed signal and the second frequency mixed signal, and output a first amplified signal and a second amplified signal; and a band-pass filter configured to filter the first amplified signal and the second amplified signal, and output a first filtered signal and a second amplified signal.