A micro-electromechanical system (MEMS) frequency divider apparatus having one or more MEMS resonators on a substrate is presented. A first oscillator frequency, as an approximate multiple of the parametric oscillation frequency, is capacitively coupled from a very closely-spaced electrode (e.g., 40 nm) to a resonant structure of the first oscillator, thus inducing mechanical oscillation. This mechanical oscillation can be coupled through additional MEMS resonators on the substrate. The mechanical resonance is then converted, in at least one of the MEMS resonators, by capacitive coupling back to an electrical signal which is a division of the first oscillation frequency. Output may be generated as a single ended output, or in response to a differential signal between two output electrodes.

A micro-electromechanical system (MEMS) frequency divider apparatus having one or more MEMS resonators on a substrate is presented. A first oscillator frequency, as an approximate multiple of the parametric oscillation frequency, is capacitively coupled from a very closely-spaced electrode (e.g., 40 nm) to a resonant structure of the first oscillator, thus inducing mechanical oscillation. This mechanical oscillation can be coupled through additional MEMS resonators on the substrate. The mechanical resonance is then converted, in at least one of the MEMS resonators, by capacitive coupling back to an electrical signal which is a division of the first oscillation frequency. Output may be generated as a single ended output, or in response to a differential signal between two output electrodes.

The present invention relates to a power management system (PMS) for multiple energy storage systems (ESS) that is for integrated management of the system having multiple ESS for controlling a frequency and having a hierarchical control structure. The PMS for ESS comprises: a plurality of ESS; a local management system (LMS) for managing one or more ESS of the plurality of ESS for each local unit; an ESS Controller (ESSC) for general management of the LMS, judging a state of the LMS and determining an output value of one or more ESS in the LMS, and transmitting the determined output value to the respective ESS; and a PMS for general management of the entire system comprising the plurality of ESS, the LMS and the ESSC, judging the state of the entire system and participating in a power grid frequency control market through a grid operator contract, controlling the output of the LMS, and adjusting a control parameter for output control.

Apparatuses and methods for providing frequency divided clocks are described. An example apparatus includes a first circuit configured to provide a first intermediate clock responsive, at least in part, to a first input clock, the first intermediate clock being lower in frequency than the first input clock and further includes a second circuit configured to provide a second intermediate clock and a third intermediate clock responsive, at least in part, to a second input clock, the second intermediate clock being complementary to the third intermediate clock and lower in frequency than the second input clock. The apparatus further includes a third circuit configured to select and provide as an output clock one of the second and third intermediate clocks responsive, at least in part, to the first and second intermediate clocks.

Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.

A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.

A local oscillator generation system includes a first frequency divider configured to divide frequencies of a first voltage controlled oscillator signal and a second voltage controlled oscillator signal by 2, and output a first divided signal and a second divided signal; a mixer configured to mix the first voltage controlled oscillator signal, the second voltage controlled oscillator signal, the first divided signal, and the second divided signal, and output a first frequency mixed signal and a second frequency mixed signal; a transimpedance amplifier configured to amplify the first frequency mixed signal and the second frequency mixed signal, and output a first amplified signal and a second amplified signal; and a band-pass filter configured to filter the first amplified signal and the second amplified signal, and output a first filtered signal and a second amplified signal.

A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.