A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.

A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.

A high-frequency oscillator comprises a reference-frequency generator and a high-frequency generator. The reference-frequency generator generates a variable reference frequency and supplies it to the high-frequency generator. The high-frequency generator comprises a phase-locked loop and generates a high-frequency signal from the variable reference frequency. The phase-locked loop comprises at least one first mixer, a second mixer and several switches. The first mixer, the second mixer and the switches are connected in series. The mixers are connected into the phase-locked loop individually in a selective manner by means of the switches.

Devices and methods may include receiving a square wave having a frequency at an input of a harmonic-cancellation (HC) sine-wave generator; receiving a clock signal having a clock frequency at a clock input of the HC sine-wave generator; generating one or more delayed square waves based on the received square wave and the clock signal using one or more delay components of the HC sine-wave generator; and amplitude-scaling the square wave and the one or more delayed square waves using a plurality of taps of the HC sine-wave generator to produce a plurality of amplitude-scaled square waves. The method may include adding the plurality of amplitude-scaled square waves using summing circuitry of the HC sine-wave generator to produce a sine wave having tone at the frequency with suppressed signal strength at selected harmonics of the frequency of the square wave at an output terminal of the HC sine-wave generator.