A system for entraining an oscillator ensemble is disclosed that includes a plurality of oscillators in an entrained phase pattern. The system includes an entrainment device operatively coupled to each non-linear oscillator of the oscillator ensemble, and the entrainment control device is configured to deliver a 2π-periodic control signal v(θ) to all oscillators of the plurality of oscillators to induce the entrained phase pattern.

A system for entraining an oscillator ensemble is disclosed that includes a plurality of oscillators in an entrained phase pattern. The system includes an entrainment device operatively coupled to each non-linear oscillator of the oscillator ensemble, and the entrainment control device is configured to deliver a 2π-periodic control signal v(θ) to all oscillators of the plurality of oscillators to induce the entrained phase pattern.

An apparatus includes an oscillation ring comprising N oscillators, where N is an even integer that is greater than 3, the N oscillators connected in series in a loop by N connection nodes, each oscillator of the N oscillators comprising a pair of cross-coupled inverting amplifiers. The apparatus also includes N inductors arranged in a star configuration such that each inductor of the N inductors connects to a corresponding connection node of the oscillation ring and a common connection node of the star configuration. The apparatus may also include N capacitor banks. Each of the N capacitor banks may include a plurality of activation switches for loading a corresponding oscillator with capacitance. A method includes providing the above apparatus and activating selected activation switches to adjust an oscillation frequency for the oscillation ring toward a desired value.

An apparatus includes an oscillation ring comprising N oscillators, where N is an even integer that is greater than 3, the N oscillators connected in series in a loop by N connection nodes, each oscillator of the N oscillators comprising a pair of cross-coupled inverting amplifiers. The apparatus also includes N inductors arranged in a star configuration such that each inductor of the N inductors connects to a corresponding connection node of the oscillation ring and a common connection node of the star configuration. The apparatus may also include N capacitor banks. Each of the N capacitor banks may include a plurality of activation switches for loading a corresponding oscillator with capacitance. A method includes providing the above apparatus and activating selected activation switches to adjust an oscillation frequency for the oscillation ring toward a desired value.

One embodiment provides a broadband signal source. The broadband signal source includes a number, n, signal paths and a combiner circuitry. Each signal path, i, includes a programmable phase shifter circuitry, an amplifier circuitry and a harmonic generation circuitry. The programmable phase shifter circuitry is configured to phase shift a path input signal by a respective phase angle, θ.sub.i. The path input signal corresponds to a source input signal having a fundamental frequency, f, and an input signal bandwidth. The amplifier circuitry is configured to amplify the phase shifted path input signal. The harmonic generation circuitry is configured to generate a path output signal including a plurality of harmonics of the amplified phase shifted path input signal. The combiner circuitry is configured to combine the number, n, path output signals to produce a broadband output signal having an output signal center frequency greater than the input signal fundamental frequency and an output signal bandwidth greater than the input signal bandwidth.

A phase-locked loop circuit comprises a multi-phase oscillator having a plurality of coupled oscillators. A calibration module detects mismatches between frequency characteristics of the different oscillators in the phase-locked loop circuit during a calibration process. The calibration module then calibrates the various oscillators to compensate for the detected mismatch. Once calibrated, the phase-locked loop circuit can operate with little or no performance degradation despite the mismatch in frequency characteristics between the different oscillators.

A phase-locked loop circuit comprises a multi-phase oscillator having a plurality of coupled oscillators. A calibration module detects mismatches between frequency characteristics of the different oscillators in the phase-locked loop circuit during a calibration process. The calibration module then calibrates the various oscillators to compensate for the detected mismatch. Once calibrated, the phase-locked loop circuit can operate with little or no performance degradation despite the mismatch in frequency characteristics between the different oscillators.

A dual-band voltage controlled oscillator (VCO) includes: a first oscillator circuit including a first inductor; a second oscillator circuit including a second inductor; a first mode switch configured to electrically connect or disconnect a first output terminal of the first oscillator circuit and a first output terminal of the second oscillator circuit; a second mode switch configured to electrically connect or disconnect a second output terminal of the first oscillator circuit and a second output terminal of the second oscillator circuit; a third mode switch configured to electrically connect or disconnect a first terminal of the first inductor and a first terminal of the second inductor; and a fourth mode switch configured to electrically connect or disconnect a second terminal of the first inductor and a second terminal of the second inductor.

There is disclosed herein integrated circuitry comprising a clock path for carrying a clock signal from a clock source to a circuit block, the circuit block being operable based on the clock signal. Clock buffer circuitry is provided along the clock path for buffering the clock signal. A tuneable inductance is connected to the clock path. A capacitor is connected to the clock path so as to form an AC coupling capacitor connected in series along the path, and is implemented between metal layers of the integrated circuitry.

There is disclosed herein integrated circuitry comprising a clock path for carrying a clock signal from a clock source to a circuit block, the circuit block being operable based on the clock signal. Clock buffer circuitry is provided along the clock path for buffering the clock signal. A tuneable inductance is connected to the clock path. A capacitor is connected to the clock path so as to form an AC coupling capacitor connected in series along the path, and is implemented between metal layers of the integrated circuitry.