Techniques are described that enables controlling the TNULL characteristic of a self-compensated oscillator by controlling the magnitude and direction of the frequency deviation versus temperature, and thus, compensating the frequency deviation.

Techniques are described that enables controlling the TNULL characteristic of a self-compensated oscillator by controlling the magnitude and direction of the frequency deviation versus temperature, and thus, compensating the frequency deviation.

The present disclosure relates to an oscillator apparatus comprising a differential transmission line forming a closed loop, a plurality of active core components that are electrically connected to the differential transmission line and that are configured to compensate for loss in the differential transmission line, a plurality of tuning elements that are electrically coupled with the differential transmission line, and a processor configured to control each tuning element of the plurality of tuning elements to activate or deactivate such that an effective electrical length of the differential transmission line is changed.

The present disclosure relates to an oscillator apparatus comprising a differential transmission line forming a closed loop, a plurality of active core components that are electrically connected to the differential transmission line and that are configured to compensate for loss in the differential transmission line, a plurality of tuning elements that are electrically coupled with the differential transmission line, and a processor configured to control each tuning element of the plurality of tuning elements to activate or deactivate such that an effective electrical length of the differential transmission line is changed.

A multiphase signal generator includes an input port. Furthermore, the multiphase signal generator includes a plurality of phase shifters. Each phase shifter of the plurality of phase shifters is configured to provide an identical phase shift Δφ. At least one phase shifter is connected to the input port. Furthermore, the multiphase signal generator includes a first phase interpolator and at least a second phase interpolator. Each phase interpolator has a respective output terminal. Each phase interpolator is configured to weight a phase of a signal at a respective first input terminal of the phase interpolator with a respective first weighting factor w.sub.i,1 and to weight a phase of another signal at a respective second input terminal of the phase interpolator with a respective second weighting factor w.sub.i,2 to generate an interpolated phase signal at the respective output terminal of the phase interpolator. A first subset of the plurality of phase shifters includes n>1 serially connected phase shifters. The first subset of phase shifters is coupled between the first input terminal and the second input terminal of the first phase interpolator. A different second subset of the plurality of phase shifters includes n serially connected phase shifters. The second subset of phase shifters is coupled between the first input terminal and the second input terminal of the second phase interpolator.

A signal specification identification apparatus includes processing circuitry that estimates the transmission rate of a received signal, performs sampling frequency conversion on the received signal, calculates a probability corresponding to each of a plurality of candidates for a specification of the received signal, selects a candidate using the respective probabilities, and calculates reliability corresponding to a selected candidate, determines whether to output the selected candidate as an identification result or perform the sampling frequency conversion again, based on the reliability, and changes a parameter indicating the ratio of the sampling frequency conversion when it is determined that the sampling frequency conversion is to be performed again. Processing is repeated until the processing circuitry determines that the selected candidate as the identification result is to be output.

Disclosed is a four-phase generation circuit, comprising a pair of input ports configured to receive a differential signal having a common mode voltage; a polyphase filter having a pair of polyphase filter input ports and first, second, third and fourth output ports; a first circuit configured to provide the differential signal with an adjusted common mode voltage to the pair of polyphase filter input ports; wherein the first, second third and fourth output ports are each configured to output a square-wave signal, with 90° phase separation between consecutive output signals; and a feedback circuit from the first, second, third and fourth outputs ports to the first circuit; wherein the feedback circuit is configured to provide a feedback signal to the first circuit to set the adjusted common mode voltage from the common mode voltage.

Quadrature oscillator circuitry, comprising: a first differential oscillator circuit having differential output nodes and configured to generate a first pair of differential oscillator signals at those output nodes, respectively; a second differential oscillator circuit having differential output nodes and configured to generate a second pair of differential oscillator signals at those output nodes, respectively; and a cross-coupling circuit connected to cross-couple the first and second differential oscillator circuits. The cross-coupling circuit may comprise a pair of cross-coupled transistors.

Quadrature oscillator circuitry, comprising: a first differential oscillator circuit having differential output nodes and configured to generate a first pair of differential oscillator signals at those output nodes, respectively; a second differential oscillator circuit having differential output nodes and configured to generate a second pair of differential oscillator signals at those output nodes, respectively; and a cross-coupling circuit connected to cross-couple the first and second differential oscillator circuits. The cross-coupling circuit may comprise a pair of cross-coupled transistors.

An analog beamformer used for array antenna and an operating method thereof are provided. The analog beamformer used for array antenna includes an intermediate-frequency amplifying circuit, multiple local oscillators, multiple mixers, multiple radio-frequency amplifying circuits, and a frequency locking circuit. The analog beamformer uses a master-oscillator and multiple slave-oscillators which embed a resonant network of frequency-and-phase-locking. The intermediate-frequency amplifying circuit receives a baseband signal to provide an intermediate-frequency signal. Power supplies or grounding ports of different local oscillators are connected together to provide multiple local-oscillating signals with consistent frequency but different phases. The mixers individually receive the intermediate-frequency signal and one of the local-oscillating signals to provide multiple mixed signals. The radio-frequency amplifying circuits receive the mixed signals to provide multiple radio-frequency signals with consistent frequency but different phases to each antenna. The frequency locking circuit only locks a frequency of one of the local-oscillating signals.