According to one embodiment, a wireless base station includes a transmitter and a receiver. The transmitter transmits a control signal and one or more operation signals to the second wireless communication terminal. The control signal instructs to transmit a signal that requests terminal-to-terminal communication between a first wireless communication terminal and the second wireless communication terminal. The operation signals are used for operating at least a part of the first wireless communication terminal. The receiver is capable of receiving at least one of a response signal or a data signal transmitted from the first wireless communication terminal to the second wireless communication terminal after the operation signals are transmitted.

A first frequency accumulator (7a) operates using an output signal of a variable frequency divider (3) as a clock. A second frequency accumulator (7b) operates using a reference signal from a reference signal source (1) as a clock. A comparison operating circuit (11) compares the output values of the first frequency accumulator (7a) and the second frequency accumulator (7b), and calculates a parameter so that a result of the comparison falls within a set value. A digital-analog converter (9) outputs a signal to be added to an output of a loop filter (6) depending on the parameter output from the comparison operating circuit (11).

A charger including a class E power driver, a frequency-shift keying (FSK) module, and a processor. The processor can receive data relating to the operation of the class E power driver and can control the class E power driver based on the received data relating to the operation of the class E power driver. The processor can additionally control the FSK module to modulate the natural frequency of the class E power transformer to thereby allow the simultaneous recharging of an implantable device and the transmission of data to the implantable device. The processor can additionally compensate for propagation delays by adjusting switching times.

A charger including a class E power driver, a frequency-shift keying (FSK) module, and a processor. The processor can receive data relating to the operation of the class E power driver and can control the class E power driver based on the received data relating to the operation of the class E power driver. The processor can additionally control the FSK module to modulate the natural frequency of the class E power transformer to thereby allow the simultaneous recharging of an implantable device and the transmission of data to the implantable device. The processor can additionally compensate for propagation delays by adjusting switching times.

A first frequency accumulator (7a) operates using an output signal of a variable frequency divider (3) as a clock. A second frequency accumulator (7b) operates using a reference signal from a reference signal source (1) as a clock. A comparison operating circuit (11) compares the output values of the first frequency accumulator (7a) and the second frequency accumulator (7b), and calculates a parameter so that a result of the comparison falls within a set value. A digital-analog converter (9) outputs a signal to be added to an output of a loop filter (6) depending on the parameter output from the comparison operating circuit (11).

A frequency modulation circuit includes a VCO, a DIV, a MIX, a single-phase differential converter, and a signal processing circuit. The signal processing circuit performs differential arithmetic processing of an intermediate frequency signal with a program of a microcomputer according to a quadrature demodulation scheme and, thereafter, measures a frequency from phase information, performs n-th order polynomial (n is an integer equal to or larger than 2) approximation on time-frequency data of an IF signal output by a chirp modulation control voltage after inverse function correction, and performs modulation correction for correcting a time error.

Provided is a technique that can generate a spread spectrum clock signal in all of an upper-spread mode, a down-spread mode, and a center-spread mode. A spread spectrum clock generator (2) spreads a spectrum of a signal with a predetermined carrier frequency to generate a spread spectrum clock signal under the control of a control unit (13). The control unit includes carrier frequency correction control means (13b). The carrier frequency correction control means shifts the predetermined carrier frequency to generate, from one spread mode, a spread spectrum clock signal of another pseudo spread mode.

A system for generating a radio frequency signal phase-locked to a reference signal. Such a system includes a rotary travelling wave oscillator including a conductive ring and a plurality of sustaining amplifying cells electrically connected to the ring; a programmable multiplexer device designed to electrically connect an input port of the system to an amplifying cell that can be selected from the cells of the plurality. The system is designed so that the oscillator generates the locked radio frequency signal when the reference signal is injected at the input port of the system. A phase difference between the radio frequency signal and the reference signal is a function of the amplifying cell to which the input port is electrically connected via the programming of the multiplexer device.

A frequency delta-sigma modulation signal output circuit includes: a phase modulation circuit configured to generate n delay signals obtained by delaying a measurement target signal, n being an integer of 2 or more, and generate a phase modulation signal by randomly selecting one of the n delay signals in synchronization with the measurement target signal; and a frequency ratio digital conversion circuit configured to generate a frequency delta-sigma modulation signal using a reference signal and the phase modulation signal.

In some embodiments, there is provided an apparatus including a common bus and a plurality of oscillatrode circuits coupled to the common bus, the plurality of oscillatrode circuits including a first oscillatrode circuit outputting a first frequency tone when a first input voltage is detected by the first oscillatrode circuit and a second oscillatrode circuit outputting a second frequency tone when a second input voltage is detected by the second oscillatrode circuit, wherein common bus carries the first frequency tone and the second frequency tone at different frequencies in a frequency division multiplex signal. Related systems, methods, and articles of manufacture are also disclosed.