Apparatuses, systems, and methods are disclosed for stochastic linear detection. A digital signal processor determines information about a plurality of transmitted signals based on a plurality of received signals. An initialization module determines an estimator matrix and a noise shaping matrix based on channel state information that relates the transmitted signals to the received signals. A sample generation module stochastically generates a plurality of signal estimates so that each signal estimate is a sum of a fixed component and a random component. The fixed component may be based on applying the estimator matrix to a vector of the received signals, and the random component may be based on applying the noise shaping matrix to generated noise. An output module sends soft information to an error-correcting code (ECC) decoder for decoding bits carried by the transmitted signals. The soft information may be based on the plurality of signal estimates.

Systems and methods for a non-data-aided (NDA) approach to advanced OFDM timing are provided. This approach allows for accurate OFDM symbol timing and synchronization by avoiding inter-symbol interference (ISI) in multipath environments where an earliest arriving signal may not be the strongest signal. The NDA approach may rely on generating and applying a bias correction to a combined correlation result of the multi-path signals.

Exemplary embodiments are disclosed of demodulator circuits for amplitude shift keying (ASK) communication demodulation. In an exemplary embodiment, a demodulator circuit is configurable (e.g., modular and/or scalable, etc.) to include any number of levels (one or more N-Levels) of demodulation. Each level of the demodulator circuit includes a peak detector, a bandpass filter, and a lowpass filter and control capacitor(s). The bandpass filter is coupled with and between the peak detector and the lowpass filter and control capacitor(s). Each level of the demodulator circuit may be identical to each other and include the same or similar components (e.g., peak detector, bandpass filter, lowpass filter and control capacitor(s)). And each demodulator circuit level (Level-1, Level-2 . . . Level-N) may be coupled with a summing voltage amplifier. The summing voltage amplifier may be coupled with an adaptive DC-offset and a lowpass filter, which, in turn, is coupled with a microcontroller.

Exemplary embodiments are disclosed of demodulator circuits for amplitude shift keying (ASK) communication demodulation. In an exemplary embodiment, a demodulator circuit is configurable (e.g., modular and/or scalable, etc.) to include any number of levels (one or more N-Levels) of demodulation. Each level of the demodulator circuit includes a peak detector, a bandpass filter, and a lowpass filter and control capacitor(s). The bandpass filter is coupled with and between the peak detector and the lowpass filter and control capacitor(s). Each level of the demodulator circuit may be identical to each other and include the same or similar components (e.g., peak detector, bandpass filter, lowpass filter and control capacitor(s)). And each demodulator circuit level (Level-1, Level-2 . . . Level-N) may be coupled with a summing voltage amplifier. The summing voltage amplifier may be coupled with an adaptive DC-offset and a lowpass filter, which, in turn, is coupled with a microcontroller.

The present application is directed to an electronic device that has a receiver configured to receive data from a second electronic device and identify potential sync header locations within a portion of the data by performing a mutually exclusive or (XOR) logic operation on a plurality of sequential pairs of bits of the data. Additionally, the receiver is configured to identify sync headers in the data by determining which of the potential sync header locations is shared in subsequent portions of the data.

A bandwidth detection device comprises a receiving circuit, for receiving a first plurality of frequency-domain signals on a first subchannel; a filter circuit, coupled to the receiving circuit, for transferring the first plurality of frequency-domain signals to a first plurality of filtered frequency-domain signals according to a filter function; and a processing circuit, coupled to the filter circuit, for comparing the first plurality of frequency-domain signals with the first plurality of filtered frequency-domain signals, to determine whether the first subchannel comprises first transmitted data.

In a PAM-N receiver, sampler reference levels, DC offset and AFE gain may be jointly adapted to achieve optimal or near-optimal boundaries for the symbol decisions of the PAM-N signal. For reference level adaptation, the hamming distances between two consecutive data samples and their in-between edge sample are evaluated. Reference levels for symbol decisions are adjusted accordingly such that on a data transition, an edge sample has on average, equal hamming distance to its adjacent data samples. DC offset may be compensated to ensure detectable data transitions for reference level adaptation. AFE gains may be jointly adapted with sampler reference levels such that the difference between a reference level and a pre-determined target voltage is minimized.

A demodulator is provided for demodulating an amplitude-modulated input signal defined by a carrier signal having a carrier frequency modulated by a modulating signal, the demodulator including an amplifier stage having a gain and structured to receive the amplitude-modulated input signal, and a gain control stage coupled to the amplifier stage and configured to vary the gain of the amplifier stage according to the carrier frequency of the carrier signal.

A demodulator is provided for demodulating an amplitude-modulated input signal defined by a carrier signal having a carrier frequency modulated by a modulating signal, the demodulator including an amplifier stage having a gain and structured to receive the amplitude-modulated input signal, and a gain control stage coupled to the amplifier stage and configured to vary the gain of the amplifier stage according to the carrier frequency of the carrier signal.

A detector circuit in which a change in a detection voltage due to temperature is suppressed is provided. The detector circuit includes a first rectification element having an anode to which an input signal is inputted. A second rectification element has a cathode connected with a cathode of the first rectification element and has an anode connected to an output terminal. A current mirror circuit for supplying a current to the first rectification element and for supplying a current-mirror current of the current to the second rectification element is included in the detector circuit.