Patent classifications
H03D3/00
ELECTRONIC ENVELOPE DETECTION CIRCUIT AND CORRESPONDING DEMODULATOR
An electronic envelope detection circuit includes an input signal detecting circuit having at least one MOS transistor configured to receive a radiofrequency input signal and to deliver an internal signal on the basis of the input signal. The biasing point of the at least one transistor is controlled by the input signal and a control signal. A processing circuit that is coupled to the input signal detecting circuit is configured to deliver a low-frequency output signal on the basis of the internal signal and further deliver the control signal on the basis of the output signal. In operation, the value of the control signal decreases when the average power of the input signal increases, and vice versa.
ELECTRONIC ENVELOPE DETECTION CIRCUIT AND CORRESPONDING DEMODULATOR
An electronic envelope detection circuit includes an input signal detecting circuit having at least one MOS transistor configured to receive a radiofrequency input signal and to deliver an internal signal on the basis of the input signal. The biasing point of the at least one transistor is controlled by the input signal and a control signal. A processing circuit that is coupled to the input signal detecting circuit is configured to deliver a low-frequency output signal on the basis of the internal signal and further deliver the control signal on the basis of the output signal. In operation, the value of the control signal decreases when the average power of the input signal increases, and vice versa.
NEAR FIELD COMMUNICATION DEVICE AND OPERATING METHOD OF NEAR FIELD COMMUNICATION DEVICE
A near field communication device configured to receive a signal from an antenna and to generate a first in-phase signal and a first quadrature-phase signal by multiplying the signal with a first oscillation signal and a second oscillation signal; a first and second low-pass filter configured to generate a second in-phase signal and a second quadrature-phase signal; a first and second analog-to-digital converter configured to generate a third in-phase signal and a third quadrature-phase signal; a digital signal extractor configured to generate a first signal and a second signal based on the third in-phase signal, the third quadrature-phase signal, a first look-up table, and a second look-up table, select one from among the first signal and the second signal based on a signal pattern, and output the selected one as an extraction signal; and a modem configured to receive the extraction signal and to demodulate the extraction signal.
RF ripple correction in an antenna aperture
A method and apparatus for RF ripple correction in an antenna aperture are described. In one embodiment, the antenna comprises: an array of antenna elements having liquid crystal (LC); drive circuitry coupled to the array and having a plurality of drivers, each driver of the plurality of drivers coupled to an antenna element of the array and operable to apply a drive voltage to the antenna element; and radio-frequency (RF) ripple correction logic coupled to the drive circuitry to adjust drive voltages to compensate for ripple.
Methods, circuits, and apparatus for calibrating an in-phase and quadrature imbalance
Methods, circuits, and apparatus for calibrating an in-phase and quadrature (IQ) imbalance of a communication signal including an in-phase component and a quadrature component in a communication apparatus, the method including determining whether to calibrate the IQ imbalance of the communication signal in the communication apparatus; selecting, in response to a determination to calibrate the IQ imbalance of the communication signal, at least one of an amplitude calibration or a phase calibration; controlling, in accordance with the selected amplitude calibration or phase calibration, at least one of an in-phase delay circuit or a quadrature delay circuit to adjust a pulse of at least one of a first LO signal or a second LO signal to thereby generate at least one pulse-adjusted LO signal; and multiplying the at least one pulse-adjusted LO signal with the communication signal to thereby calibrate the IQ imbalance.
Combined radar and communications system using common signal waveform
A system having a set of common hardware and common signal processing together with a common waveform family that can be used to achieve both efficient radar and efficient communications functions. The system includes a common radar/communications transmitter having a transmission antenna and a combined radar and communications receiver having a common reception antenna. The common radar/communications transmitter is configured to transmit combined radar/communications waveform-modulated signals comprising symbols, each symbol consisting of an up chirp and a down chirp. The combined radar and communications receiver includes a baseband radar signal processing module configured to estimate range and range rate of a radar object from the received symbols and a baseband communications signal processing module configured to detect slopes and initial phases of the up and down chirps of each received symbol.
Electronic envelope detection circuit and corresponding demodulator
An electronic envelope detection circuit includes an input signal detecting circuit having at least one MOS transistor configured to receive a radiofrequency input signal and to deliver an internal signal on the basis of the input signal. The biasing point of the at least one transistor is controlled by the input signal and a control signal. A processing circuit that is coupled to the input signal detecting circuit is configured to deliver a low-frequency output signal on the basis of the internal signal and further deliver the control signal on the basis of the output signal. In operation, the value of the control signal decreases when the average power of the input signal increases, and vice versa.
Electronic envelope detection circuit and corresponding demodulator
An electronic envelope detection circuit includes an input signal detecting circuit having at least one MOS transistor configured to receive a radiofrequency input signal and to deliver an internal signal on the basis of the input signal. The biasing point of the at least one transistor is controlled by the input signal and a control signal. A processing circuit that is coupled to the input signal detecting circuit is configured to deliver a low-frequency output signal on the basis of the internal signal and further deliver the control signal on the basis of the output signal. In operation, the value of the control signal decreases when the average power of the input signal increases, and vice versa.
IQ mismatch correction module
An IQ estimation module comprising a powerup state IQ estimator configured to generate powerup state IQ estimates based on a powerup calibration of the IQ estimation module, a steady state IQ estimator configured to generate steady state IQ estimates during a steady state operation of the IQ estimation module, and an IQ estimate extender configured to determine differences between the powerup state IQ estimates and steady state IQ estimates at their respective frequency bins and adjust the powerup state IQ estimates to improve the accuracy of IQ estimates.
Parallel voltage and current multiple amplitude shift key demodulation
Systems, methods and apparatus for wireless charging are disclosed. A method for decoding data includes demodulating voltage or current waveform in each tank circuit of a plurality of inductive power transfer circuits to obtain at least one demodulated signal from each tank circuit, capturing a bit sequence from each demodulated signal by clocking signal state of each demodulated signal through a direct memory access (DMA) circuit, streaming bit sequences received from the DMA circuit into a plurality of data streams, and decoding one or more messages from the plurality of data streams.