An interpolator includes a first delay circuit, a second delay circuit, and a tunable delay circuit. The first delay circuit delays a first input signal for a fixed delay time, so as generate a first output signal. The second delay circuit delays a second input signal for the fixed delay time, so as to generate a second output signal. The tunable delay circuit delays the first input signal for a tunable delay time, so as to generate an output interpolation signal. The tunable delay time is determined according to the first output signal, the second output signal, and the output interpolation signal.

An integrated circuit device includes: an AFE circuit (analog front-end circuit) that receives a first signal and a second signal, carries out waveform shaping of the first signal and waveform shaping of the second signal, outputs the first signal whose waveform is shaped to a first signal line, and outputs the second signal whose waveform is shaped to a second signal line; and a time-to-digital converter that receives the first signal from the AFE circuit via the first signal line, receives the second signal from the AFE circuit via the second signal line, and converts a time difference between transition timings of the first signal and the second signal into a digital value. At least one of the first signal line and the second signal line has redundant wiring for isometric wiring.

An integrated circuit device includes: an AFE circuit (analog front-end circuit) that receives a first signal and a second signal, carries out waveform shaping of the first signal and waveform shaping of the second signal, outputs the first signal whose waveform is shaped to a first signal line, and outputs the second signal whose waveform is shaped to a second signal line; and a time-to-digital converter that receives the first signal from the AFE circuit via the first signal line, receives the second signal from the AFE circuit via the second signal line, and converts a time difference between transition timings of the first signal and the second signal into a digital value. At least one of the first signal line and the second signal line has redundant wiring for isometric wiring.

Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.

Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.

Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.

A clock receiver including: a ring oscillator adapted to generate a clock signal, the ring oscillator having a sequence of N inverters, an input of a first inverter being coupled to a feedback node, an input of a second inverter being connected to an output of the first inverter and to an input line for receiving a reference clock signal, and an output of the second inverter or of a third inverter providing a first phase signal; a further sequence of inverters, an input of a first further inverter being coupled to the feedback node, and an output of another further inverter providing a second phase signal; and a control circuit for adjusting an oscillation frequency of the ring oscillator based on the relative phases of the first and second phase signals.

A clock receiver including: a ring oscillator adapted to generate a clock signal, the ring oscillator having a sequence of N inverters, an input of a first inverter being coupled to a feedback node, an input of a second inverter being connected to an output of the first inverter and to an input line for receiving a reference clock signal, and an output of the second inverter or of a third inverter providing a first phase signal; a further sequence of inverters, an input of a first further inverter being coupled to the feedback node, and an output of another further inverter providing a second phase signal; and a control circuit for adjusting an oscillation frequency of the ring oscillator based on the relative phases of the first and second phase signals.

Embodiments of a phase difference estimator and method are generally described herein. The phase difference estimator includes a delay element to delay a reference clock signal that includes an alternating symbol waveform by one of a plurality of delay values. The phase difference estimator further includes a sampler to sample a monitored clock signal provided by a second device responsive to edges of the delayed reference clock signal to generate a sampled signal output. The phase difference estimator further includes a correlation element to correlate the sampled signal output of the sampler with a step function to generate a correlation value for each delay value, and a controller to instruct the delay element to delay the reference clock signal by one of the delay values and provide a phase difference estimate output indicative of a phase difference between the reference and monitored clock signals based on the correlation value.

Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.