A switched capacitor amplifier circuit includes an operational amplifier, a first capacitor and a second capacitor each having one end connected to a negative input terminal of the operational amplifier, a first switching circuit configured to connect the other end of the first capacitor and a signal source during a first operation, a second switching circuit configured to connect the other end of the second capacitor and the output terminal of the operational amplifier so as to connect the output terminal and the negative input terminal of the operational amplifier through the second capacitor during the second operation, and an impedance converter circuit configured to convert an output impedance of the signal source into a specified impedance, the impedance converter circuit being connected between the first switching circuit and the other end of the first capacitor.

The disclosed technology can include a power amplifier comprising an input, an output, and a transformer. The power amplifier can include a primary inductor coil coupled to the input, a secondary inductor coil coupled to the output, and three harmonic branches coupled to the primary coil. Each branch can comprise at least one electrical component having a tunable impedance.

Disclosed is an apparatus including a radio frequency amplifying circuit, a power supply circuit, and a bias generating circuit. The power supply circuit includes: a first power supply terminal coupled to a first ground terminal via a first capacitor and coupled to/decoupled from the radio frequency amplifying circuit through a first switch; and a second power supply terminal coupled to a second ground terminal via a second capacitor and coupled to/decoupled from the radio frequency amplifying circuit through a second switch, wherein the first capacitor and second capacitor are coupled to/decoupled from the radio frequency amplifying circuit through the first switch and second switch respectively, the supply voltages outputted from the two power supply terminals are different, and the two switches are not concurrently turned on. The radio frequency amplifying circuit operates according to a bias voltage provided by the bias generating circuit and one of the two supply voltages.

A signal processing circuit, which has a pair of input nodes and a pair of output nodes, includes a first switch pair, a second switch pair, an amplifier, a first compensation capacitor and a second compensation capacitor. The first switch pair is coupled between the pair of input nodes and a plurality of floating nodes. The second switch pair is coupled between the plurality of floating nodes and the pair of output nodes. The amplifier is coupled between the plurality of floating nodes and the pair of output nodes. The first compensation capacitor is coupled between a first floating node among the plurality of floating nodes and a first output node among the pair of output nodes. The second compensation capacitor is coupled between a second floating node among the plurality of floating nodes and the first output node.

In an embodiment an integration circuit has a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, an output terminal to provide an output signal as a function of the first and the second input signal, a first and a second amplifier, each being switchably connected between the first or the second input terminal and the output terminal, and a capacitor which is switchably coupled in a feedback loop either of the first or of the second amplifier such that the capacitor and one of the first and the second amplifier form an inverting integrator providing the output signal. Therein the integration circuit is prepared to be operated in a first and a second subphase, wherein in each of first and second subphases one of the first and the second input signals is supplied to the inverting integrator and the respective other one of first and the second input signals is supplied to the respective other one of the first and the second amplifier.

A device of integration of an electric current received on an integration node, includes an operational amplifier, an integration capacitor, and a circuit for modifying an output voltage of the operational amplifier formed by a charge transfer circuit configured to be connected on the integration node and to transfer charges into the integration capacitor. The device also includes a comparison circuit configured to trigger the modification circuit at least once during the integration duration, and a storage circuit configured to store the number of triggerings which have occurred during the integration duration. The received electric current is calculated according to the output voltage as well as to the number of triggerings multiplied by the modification of the output voltage induced by the modification circuit.

In high data rate receivers, comprising a photodetector (PD) and a transimpedance amplifier (TIA), a transmitted optical signal typically has poor extinction ratio, which translates into a small modulated current with a large DC current at the output of the PD. The large DC current saturates the TIA, which significantly degrades the gain and bandwidth performance. Accordingly, cancelling photo diode DC current in high data rate receivers is important for proper receiver operation. A DC current cancellation loop, comprising a low pass filter section and a trans-conductance cell (GM) are connected to the input of the TIA. PD DC current I.sub.DC is drawn from the input node of the TIA in the GM cell, such that the cancellation loop maintains the DC voltage value of the TIA input node to be the same as a reference voltage (V.sub.REF).

A signal coupling method and apparatus is disclosed. A coupling network is coupled to convey signals from first functional circuit block to a second functional circuit block. The coupling network includes a first signal path having a first capacitor for providing AC coupling between the first and second functional circuit blocks. The coupling network further includes a second signal path in parallel with the first signal path. The second signal path includes a switched capacitor circuit coupled to receive a first common mode voltage corresponding to the first functional circuit block and a second common mode voltage corresponding to the second functional circuit block.

A push-pull dynamic amplifier is operable in reset and amplification phases. The amplifier includes first NMOS and PMOS input transistors that are electrically coupled to a first input terminal and a first output terminal. Second NMOS and PMOS input transistors are electrically coupled to a second input terminal and a second output terminal. First and second reset switches are electrically coupled to the first and second output terminals, respectively. A power supply switch is electrically coupled to the first and the second PMOS transistors, and a ground switch is electrically coupled to the first and the second NMOS transistors. During the reset phase, the reset switches are closed and the power supply switch and the ground switch are opened. During the amplification phase, the reset switches are opened and the power supply switch and the ground switch are closed.

A signal processing circuit that achieves functionality similar to that of a switched capacitor circuit without the necessity a clock. The circuit compensates for finite open loop gain and for offset voltages in the components, allowing the circuit to calculate the result of a problem represented by the circuit essentially immediately upon the presentation of a new input or set of inputs. After the circuit is initialized to remove gain, an input is applied to the circuit, and propagates through the network and affects the state of amplifier outputs; the propagation from the input through capacitors to the ultimate output(s) of the circuit is the analog calculation taking place. The calculation is not mediated by a clock, but rather the calculation corresponds to the circuit's one-time response to the application of the inputs. Using these techniques complex signal processing circuits and even analog neural networks may be constructed.