Disclosed herein are signal amplifier architectures that provide a plurality of gain modes. Different gain modes can use different paths through the amplifier architecture. Switches that are used to select the path through the amplifier architecture can be configured to also provide targeted impedance in a degeneration block or matrix. The switches that select the gain path are provided in the amplifier architecture and are thus not needed or used in the degeneration block, thereby reducing the size of the package for the amplifier architecture, improving the noise figure (NF), improving impedance matching, and eliminating the need for control logic associated with the degeneration block or matrix.

A method and network equipment for controlling power amplification are disclosed. The method for controlling power amplification includes outputting a voltage signal according to the state of network equipment. When the network equipment is in an idle state, at least one power amplifier transistor is switched off according to a voltage signal.

A method and network equipment for controlling power amplification are disclosed. The method for controlling power amplification includes outputting a voltage signal according to the state of network equipment. When the network equipment is in an idle state, at least one power amplifier transistor is switched off according to a voltage signal.

An amplifier includes an amplification circuit, an equalization circuit, an output circuit, a first gain adjusting circuit, and a second gain adjusting circuit. The amplification circuit changes voltage levels of first and second amplification nodes based on first and second input signals. The equalization circuit changes the voltage levels of the first and second amplification nodes. The output circuit generates an output signal based on the voltage levels of the first and second amplification nodes. The first gain adjusting circuit changes voltage levels applied to the first and second amplification nodes based on the voltage levels of the first and second amplification nodes and a first gain control signal. The second gain adjusting circuit changes a voltage level of the output signal based on a second gain control signal.

Analog multipliers can perform signal processing with approximate precision asynchronously (clock free) and with low power consumptions, which can be advantageous including in emerging mobile and portable artificial intelligence (AI) and machine learning (ML) applications near or at the edge and or near sensors. Based on low cost, mainstream, and purely digital Complementary-Metal-Oxide-Semiconductor (CMOS) manufacturing process, the present invention discloses embodiments of current-mode analog multipliers that can be utilized in multiply-accumulate (MAC) signal processing in end-application that require low cost, low power consumption, (clock free) and asynchronous operations.

An active current source load of a fully differential amplifier which is converted into a transconductance (g.sub.m) component also at higher frequency by feed-forwarding input signals to their gates. With signal coupling to gate, unity gain bandwidth (UGB) of the amplifier increases by a factor of two. In addition to this, the signal is coupled to source as well to achieve three-fold UGB enhancement. Thus, the effective trans-conductance is g.sub.mp at dc and becomes g.sub.mp+(g.sub.mn.sub.gate+g.sub.mn.sub.src) at high frequency which triples the UGB when g.sub.mp=g.sub.mn.sub.gate/src.

A driver circuit arrangement for driving a load and a differential drive arrangement thereof are provided. The driver circuit arrangement employs a dual feedback configuration with a feedback resistor and a current sensor feedback arrangement. The current sensor feedback arrangement provides a current feedback path from the amplifier output to the amplifier input, and has a current sensor resistor connected in an output current path of the driver circuit arrangement. A current feedback amplifier is present connected to the current sensor resistor and to the amplifier input.

A variable gain amplifier includes a differential amplifier circuit having a pair of input terminals and a pair of output terminals, and a first variable attenuation circuit connected between at least one of the pair of input terminals and the pair of output terminals of the differential amplifier circuit and capable of switching a resistance value on the basis of a control signal which is input from the outside.

Techniques for controlling one or more audio amplifiers in or associated with a device coupled on a local area network are disclosed. An example playback device includes a processor, an amplifier, a network interface, and a memory. The memory includes a software module that, when executed by the processor, causes the playback device to: operate in a first power mode in which the amplifier consumes a first amount of power; while operating in the first power mode, determine that a defined time has passed since receiving, via the network interface, a specified type of data packet; and based on determining that the defined time has passed since receiving the specified type of data packet, transition from operating in the first power mode to operate in a second power mode in which the amplifier consumes a second amount of power, wherein the first amount of power is greater than the second amount of power.

An amplifier includes an amplification circuit, an equalization circuit, an output circuit, a first gain adjusting circuit, and a second gain adjusting circuit. The amplification circuit changes voltage levels of first and second amplification nodes based on first and second input signals. The equalization circuit changes the voltage levels of the first and second amplification nodes. The output circuit generates an output signal based on the voltage levels of the first and second amplification nodes. The first gain adjusting circuit changes voltage levels applied to the first and second amplification nodes based on the voltage levels of the first and second amplification nodes and a first gain control signal. The second gain adjusting circuit changes a voltage level of the output signal based on a second gain control signal.