Patent classifications
H03G1/00
Radio transmitter
In a gain control device, a gain control voltage adjust circuit includes a time-constant circuit and outputs an adjusted gain control voltage depending on an adjustment signal and a control voltage generated by a differential amplifier upon input of the adjustment signal. An adjustment signal generation circuit outputs the adjustment signal during an adjustment signal output period. This period is a specified period before a first burst signal is output from a signal output unit and where a burst signal is not output from the signal output unit. The adjustment signal is to make the adjusted gain control voltage closer to a target voltage. The target voltage is a gain control voltage output from the gain control voltage adjust circuit and corresponding to a steady part of a second burst signal. The second burst signal is a burst signal output before the first burst signal.
Radio frequency switch
A radio frequency switch is disclosed. The RF switch uses a combination of transistor technology and a topology to create an RF switch that has a high isolation and a high voltage breakdown at frequencies including those above a gigahertz.
Output stage circuit, operational amplifier, and signal amplifying method capable of suppressing variation of output signal
An output stage circuit of an operational amplifier, the operational amplifier, and a signal amplifying method applied to the operational amplifier are provided. The output stage circuit includes an inverting circuit and a compensation module. The inverting circuit is electrically connected to a gain stage circuit of the operational amplifier. The inverting circuit generates an output signal of the operational amplifier. The compensation module includes a first compensation circuit, including a first current providing path and a first suppression activation circuit. The first current providing path provides a first compensation current. The first suppression activation circuit conducts the first compensation current to the inverting circuit if a first compensation condition related to a first gain stage signal generated by the gain stage circuit is satisfied. Variation of the output signal is suppressed because of the first compensation current.
Variable gain amplifier
A variable gain amplifier circuit is disclosed. In one embodiment, an amplifier circuit includes first and second stages. Each stage includes one or more inverter pairs, with one inverter of each pair coupled to receive an inverting component of a differential signal and the other inverter of the pair coupled to receive a non-inverting component. The first stage receives a differential input signal and produces an intermediate differential signal. The second stage receives the intermediate differential signal and produces a differential output signal, the differential output signal being an amplified version of the differential input signal.
Method and system for linearizing an amplifier using transistor-level dynamic feedback
The present disclosure describes a method and system for linearizing an amplifier using transistor-level dynamic feedback. The method and system enables nonlinear amplifiers to exhibit linear performance using one or more of gain control elements and phase shifters in the feedback path. The disclosed method and system may also allow an amplifier to act as a pre-distorter or a frequency/gain programmable amplifier.
Dimming LED circuit augmenting DC/DC controller integrated circuit
Embodiments include systems, methods, and apparatuses for providing a dimming function in a single stage AC input light emitting diode (LED) driver with a controller that contains an on-chip error amplifier and an on-chip fixed reference voltage source coupled to a first input of the error amplifier. The controller controls a duty cycle of a switching transistor to cause a feedback voltage, applied to a first package input terminal, to match the reference voltage. To achieve a dimming function, a voltage across a current sense resistor in series with the LEDs is applied to a first input of a high gain differential amplifier, and a variable dimming control voltage is applied to a second input of the differential amplifier. The output of the differential amplifier is coupled to the first package input terminal. The differential amplifier input signals will be matched at the target LED current level.
Flame scanner having non-linear amplifier with temperature compensation
An amplifier assembly (100) includes an amplifier (102) having an input terminal, an output terminal and a feedback terminal; a first feedback path connecting the output terminal to the feedback terminal; a second feedback path connecting the output terminal to the feedback terminal; a switch (124) positioned in the second feedback path, the switch (124) opening or closing in response to a voltage at the output terminal relative to a breakpoint, when the switch (124) is open, the amplifier assembly (100) has a first gain and when the switch (124) is closed, the amplifier assembly (100) has a second gain; and a thermally variable element (152) connected to the switch (124), the thermally variable element (152) configured to generate a compensation voltage to maintain the breakpoint in response to varying temperature of the switch (152).
Multi-mode amplifier architectures with resonant structures
The disclosed technology is related to a radio-frequency (RF) amplifier having a bypass circuit and a resonant structure to improve performance in a bypass mode (e.g., a low gain mode). The disclosed amplifiers have a resonant structure that effectively isolates an amplifier core from a bypass circuit. For example, in a bypass mode, the resonant structure is configured to create an open impedance looking into the amplifier core input. This effectively removes any loading from the amplifier core to the bypass circuit. The disclosed amplifiers with resonant structures improve linearity performance in bypass modes due at least in part to the open impedance to the amplifier core provided by the resonant structure.
Variable gain amplifier including impedance ladder circuit with exponentially dependent degeneration resistance
A variable gain amplifier includes input terminals configured to receive a differential input of the variable gain amplifier, output terminals configured to generate a differential output of the variable gain amplifier, the differential output having a gain applied by the variable gain amplifier to the differential input, and an impedance ladder circuit coupled to the input terminals, the impedance ladder circuit comprising a plurality of semiconductor switches configured to receive respective control signals based on a control voltage. The plurality of semiconductors switches are responsive to the respective control signals to adjust the gain of the variable gain amplifier and configured with a predetermined exponential scale such that the impedance ladder circuit causes a slope of the gain of the variable gain amplifier relative to the control voltage to be generally linear.
Elementary cell and charge pumps comprising such an elementary cell
The elementary pumping cell comprises an input (E) receiving an input voltage (Vin), a clock terminal (H) receiving a first clock signal (CK1) and an output (S), a first capacitor (C1) having a first terminal connected to the clock terminal and a second terminal, a first transistor (A1) having a first source/drain terminal coupled to the input, a second source/drain terminal and a gate terminal, a second transistor (A2) having a first source/drain terminal, a second source/drain terminal coupled to the input and a gate terminal coupled to the second terminal of the first capacitor, a third transistor (A3) having a first source/drain terminal coupled to the first source/drain terminal of the second transistor, a second source/drain terminal coupled to the gate terminal of the second transistor and a gate terminal coupled to the input, and a fourth transistor (A4) having a first source/drain terminal coupled to the second source/drain terminal of the first transistor, a second source/drain terminal coupled to the first source/drain terminal of the second and third transistors and a gate terminal coupled to the input. The gate terminal of the first transistor is coupled to the gate terminal of the second transistor.