A transmit/receive switching circuit implementation reduces transmitting/receiving switching losses in a transceiver during different modes of operation. The implementation includes connecting a low noise amplifier and a power amplifier in accordance with a shunt configuration in the transceiver. The implementation also includes disabling the power amplifier to achieve a high impedance state by grounding an output stage bias and enabling the low noise amplifier and disabling one or more transistors connected to a path between the low noise amplifier and the power amplifier during a receive mode.

Disclosed herein are methods for amplifying a signals. The methods include receiving signals at a plurality of input nodes. The methods also include configuring a gain stage to be in a selected one of a plurality of gain settings, at least some of the gain settings resulting in different impedances presented to the signal. The methods also include adjusting the resistance presented to the signal by the gain stage for the selected gain setting, the adjusted resistance being configured to provide a targeted constant value of the impedance at the input across the plurality of gain settings. The methods also include amplifying at least a portion of the received signals. Adjusting the resistance compensates for changes to the input impedance to improve return loss and mismatch over gain modes.

An RF receiver circuit configuration and design limited by conditions and frequencies to simultaneously provide steady state low-noise signal amplification, frequency down-conversion and image signal rejection. The invention provides combined circuits of an RF transceiver architecture that measure antenna reflected power relative to forward power using the error amplifier signal to adjust the gain of the variable gain amplifier in order to compensate for the mismatch between forward reflected power and forward power at the antenna in order to achieve constant radiated power. The RF receiver circuit may be implemented as one of a CMOS single chip device or as part of an integrated system of CMOS components.

The exemplified disclosure presents a highly power efficient amplifier (e.g., front-end inverter and/or amplifier) that achieves significant current reuse (e.g., 6-time for a 3-stack embodiments) by stacking inverters and splitting the capacitor feedback network. In some embodiments, the exemplified technology facilitates N-time current reuse to substantially reduced power consumption. It is observed that the exemplified disclosure facilitates significant current-reuse operation that significantly boost gain gm while providing low noise performance without increasing power usage. In addition, the exemplified technology is implemented such that current reuse and number of transistor has a generally linear relationship and using fewer transistors as compared to known circuits of similar topology.

An RF receiver circuit configuration and design is limited by conditions and frequencies to simultaneously provide steady state low-noise signal amplification, frequency down-conversion, and image signal rejection. The RF receiver circuit may be implemented as one of a CMOS single chip device or as part of an integrated system of CMOS components.

An embodiment attenuator includes a plurality of circuits coupled in series. A respective circuit includes a first capacitor connected between an input node of the respective circuit and an output node of the respective circuit, and a second capacitor connected between the output node of the respective circuit and a reference node. The output node of the respective circuit, other than a last circuit of the plurality of circuits, is connected to the input node of a successive circuit. The attenuator further includes a plurality of selectors, in which the respective circuit is associated with a respective selector that is coupled between the output node of the respective circuit and an output node of the attenuator.

A number of biasing circuits for amplifiers including voltage controlled amplifier is presented. Also a number of field effect transistor circuits include voltage controlled attenuators or voltage controlled processing circuits. Example circuits include modulators, lower distortion variable voltage controlled resistors, sine wave to triangle wave converters, and or servo controlled biasing circuits.

An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

An apparatus includes a first half-cell, a second half cell and a multiplexer. The first half-cell may comprise a first input stage configured to present a first input signal to a first auto-zero stage. The second half-cell may comprise a second input stage configured to present a second input signal to a second auto-zero stage. The multiplexer may receive a first output from the first auto-zero stage, receive a second output from the second auto-zero stage and present one of the first output and the second output. The first half-cell and the second half-cell may implement a capacitive coupling. The capacitive coupling may provide a rail-to-rail common-mode input range. The first half-cell and the second half-cell may prevent a mismatch between data signals and clock signals. The first half-cell and the second half-cell may each be configured to implement a calibration when idle.

A radio frequency switch is disclosed. The RF switch uses a combination of transistor technology and a topology to create an RF switch that has a high isolation and a high voltage breakdown at frequencies including those above a gigahertz.