In some embodiments, a method for processing an audio signal in an audio processing apparatus is disclosed. The method includes receiving an audio signal and a parameter, the parameter indicating a location of an auditory event boundary. An audio portion between consecutive auditory event boundaries constitutes an auditory event. The method further includes applying a modification to the audio signal based in part on an occurrence of the auditory event. The parameter may be generated by monitoring a characteristic of the audio signal and identifying a change in the characteristic.

In some embodiments, a method for processing an audio signal in an audio processing apparatus is disclosed. The method includes receiving an audio signal and a parameter, the parameter indicating a location of an auditory event boundary. An audio portion between consecutive auditory event boundaries constitutes an auditory event. The method further includes applying a modification to the audio signal based in part on an occurrence of the auditory event. The parameter may be generated by monitoring a characteristic of the audio signal and identifying a change in the characteristic.

A variable attenuation device includes: a first variable attenuator configured to receive a first signal through a first input end, attenuate the first signal by an amount of attenuation according to a control voltage, and output the attenuated first signal through a first output end, the first signal being one of a pair of differential signals having a 180-degree phase difference; a second variable attenuator configured to receive a second signal through a second input end, attenuate the second signal by the amount of attenuation according to the control voltage, and output the attenuated second signal through a second output end, the second signal being the other one of the pair of differential signals; a first signal distributer configured to distribute the second signal to the first output end; and a second signal distributer configured to distribute the first signal to the second output end.

An equalizer circuit includes a variable gain equalizer circuit. A third transistor MN for gain adjustment is coupled between a source of a first transistor that constitutes an input differential pair of the variable gain equalizer circuit, and a first current source IB. A fourth transistor MN for gain adjustment is coupled between a source of a second transistor that constitutes the input differential pair, and a second current source IB. A first bias voltage Vb is supplied to the gates of the third transistor MN and the fourth transistor MN, so as to enable DC gain control of the variable gain equalizer circuit.

Aspects and examples described herein provide a variable gain amplifier circuit and assembly. In one example, a variable gain amplifier circuit includes a signal input, a signal output, and a variable gain amplifier including a plurality of unit cell groups coupled between the signal input and the signal output, the variable gain amplifier configured to provide an adjustable gain to a signal received at the signal input during each of a plurality of amplify modes of the variable gain amplifier, each of the plurality of amplify modes corresponding to at least one unit cell group of the plurality of unit cell groups. A bypass path including a fixed attenuator is coupled in parallel with the variable gain amplifier between the signal input and the signal output to selectively couple the signal input to the signal output through the fixed attenuator during a bypass mode.

A programmable gain amplifier that comprises: a transconductance amplifier, a switch leakage compensation circuit and a transimpedance amplifier. The transconductance amplifier provides a transconductance amplifier current signal and includes a switchable resistance network. The switch leakage compensation circuit provides a compensation current signal and comprises a switchable compensation resistance network. The transimpedance amplifier provides the output voltage signal based on the difference between the transconductance amplifier current signal and the compensation current signal. The switchable compensation resistance network comprises a plurality of branches in parallel with each other, wherein each branch includes: a gain-mimicking switch that has a corresponding gain-setting switch in the switchable resistance network; and a leakage-current-conducting switch in series with the gain-mimicking switch. The leakage-current-conducting switch is openable and closable in accordance with the complement of a switch control signal that is used to control the gain-mimicking switch in the same branch.

A digital predistortion (DPD) system includes an input configured to receive an input signal. In some examples, a first signal path configured to generate a first signal based on the input signal. In some examples, an error model provider configured to generate an error model signal modeled after a gate bias error voltage associated with the DPD system. In some examples, a first combiner configured to combine the first signal and the error model signal to generate a first intermediate signal, and the DPD system generates an output signal based at least on the first intermediate signal.

A high-frequency power amplifier is configured in such a way as to include an input matching circuit, an amplifying element, an output matching circuit, a coupling circuit, a detection circuit, and an output terminal, and in such a way that either the input matching circuit or the output matching circuit has an active element, the detection circuit receives a signal outputted by the coupling circuit and outputs a control voltage into which the detection circuit converts the signal to the active element, and the active element changes the impedance of the active element in accordance with the control voltage outputted by the detection circuit, thereby changing the power of a signal outputted by either the input matching circuit having the active element or the output matching circuit having the active element, to change the power of a signal which the coupling circuit outputs to the output terminal.

A clamping circuit that may be used to provide efficient and effective voltage clamping in an RF front end. The clamping circuit comprises two series coupled signal path switches and a bypass switch coupled in parallel with the series coupled signal path switches. A diode is coupled from a point between the series coupled signal path switches to a reference potential. In addition, an output selection switch within an RF front end has integrated voltage clamping to more effectively clamp the output voltage from the RF front end. Additional output clamping circuits can be used at various places along a direct gain signal path, along an attenuated gain path and along a bypass path.

Disclosed herein are embodiments of a wide bandwidth attenuator circuit having a tunable gain and tunable input impedance. In some embodiments, the wideband attenuator circuit comprises a serial capacitor shunted to ground by a plurality of circuit slices that are connected in parallel and switchably coupled to the output node of the attenuator. Each circuit slice has a tunable resistor that can be set to a conductive state (enabled) or a high impedance state (disabled) The number of enabled circuit slices that are connected in parallel may be used to program the attenuator gain and the attenuator impedance.